70 {
71 {
72 .spi_bus = &SPID3,
73 .spi_config = {
74 .circular = false,
75#ifdef _CHIBIOS_RT_CONF_VER_6_1_
76 .end_cb = nullptr,
77#else
78 .slave = false,
79 .data_cb = nullptr,
80 .error_cb = nullptr,
81#endif
82
83 .ssport = GPIOA,
84 .sspad = 15,
85 .cr1 =
86 SPI_CR1_16BIT_MODE |
87 SPI_CR1_SSM |
88 SPI_CR1_SSI |
89 ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) |
90 SPI_CR1_MSTR |
91 SPI_CR1_CPHA |
92 0,
93 .cr2 = SPI_CR2_16BIT_MODE
94 },
95 .direct_io = {
96 { .port = GPIOD, .pad = 3 },
97 { .port = GPIOD, .pad = 11 },
98 { .port = GPIOA, .pad = 9 },
99 { .port = GPIOD, .pad = 10 }
100 },
103 },
104 {
105 .spi_bus = &SPID3,
106 .spi_config = {
107 .circular = false,
108#ifdef _CHIBIOS_RT_CONF_VER_6_1_
109 .end_cb = nullptr,
110#else
111 .slave = false,
112 .data_cb = nullptr,
113 .error_cb = nullptr,
114#endif
115
116 .ssport = GPIOB,
117 .sspad = 12,
118 .cr1 =
119 SPI_CR1_16BIT_MODE |
120 SPI_CR1_SSM |
121 SPI_CR1_SSI |
122 ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) |
123 SPI_CR1_MSTR |
124 SPI_CR1_CPHA |
125 0,
126 .cr2 = SPI_CR2_16BIT_MODE
127 },
128 .direct_io = {
129 { .port = GPIOA, .pad = 8 },
130 { .port = GPIOD, .pad = 15 },
131 { .port = GPIOD, .pad = 2 },
132 { .port = NULL, .pad = 0 }
133 },
136 },
137 {
138 .spi_bus = &SPID3,
139 .spi_config = {
140 .circular = false,
141#ifdef _CHIBIOS_RT_CONF_VER_6_1_
142 .end_cb = nullptr,
143#else
144 .slave = false,
145 .data_cb = nullptr,
146 .error_cb = nullptr,
147#endif
148
149 .ssport = GPIOE,
150 .sspad = 1,
151 .cr1 =
152 SPI_CR1_16BIT_MODE |
153 SPI_CR1_SSM |
154 SPI_CR1_SSI |
155 ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) |
156 SPI_CR1_MSTR |
157 SPI_CR1_CPHA |
158 0,
159 .cr2 = SPI_CR2_16BIT_MODE
160 },
161 .direct_io = {
162 { .port = GPIOD, .pad = 12 },
163 { .port = GPIOD, .pad = 14 },
164 { .port = NULL, .pad = 0 },
165 { .port = GPIOA, .pad = 10 }
166 },
169 }
170};