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hal_lld.h
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1/*
2 ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file KE1xF/hal_lld.h
19 * @brief Kinetis KE1xF HAL subsystem low level driver header.
20 * @author andreika <prometheus.pcb@gmail.com>
21 *
22 * @addtogroup HAL
23 * @{
24 */
25
26#ifndef HAL_LLD_H_
27#define HAL_LLD_H_
28
29#include "kinetis_registry.h"
30#include "kinetis_dma.h"
31#include "kinetis_stm32.h"
32
33/*===========================================================================*/
34/* Driver constants. */
35/*===========================================================================*/
36
37/**
38 * @brief Defines the support for realtime counters in the HAL.
39 */
40#define HAL_IMPLEMENTS_COUNTERS FALSE
41
42/**
43 * @name Platform identification
44 * @{
45 */
46#define PLATFORM_NAME "Kinetis"
47/** @} */
48
49/**
50 * @name Internal clock sources
51 * @{
52 */
53#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
54#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
55/** @} */
56
57#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
58#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
59#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
60#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
61#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
62#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
63#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
64#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
65
66/*===========================================================================*/
67/* Driver pre-compile time settings. */
68/*===========================================================================*/
69
70/**
71 * @name Configuration options
72 * @{
73 */
74/**
75 * @brief Disables the MCG/system clock initialization in the HAL.
76 */
77#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
78#define KINETIS_NO_INIT FALSE
79#endif
80
81/**
82 * @brief MCG mode selection.
83 */
84#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
85#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
86#endif
87
88/**
89 * @brief MCU PLL clock frequency.
90 */
91#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
92#define KINETIS_PLLCLK_FREQUENCY 96000000UL
93#endif
94
95/**
96 * @brief Clock divider for core/system clocks (OUTDIV1).
97 * @note The allowed range is 1..16
98 * @note The default value is calculated for a 48 MHz system clock
99 * from a 96 MHz PLL output.
100 */
101#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
102 #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
103 #define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
104 #else
105 #define KINETIS_CLKDIV1_OUTDIV1 2
106 #endif
107#endif
108
109/**
110 * @brief Clock divider for bus clock (OUTDIV2).
111 * @note The allowed range is 1..16
112 * @note The default value is calculated for a 48 MHz bus clock
113 * from a 96 MHz PLL output.
114 */
115#if !defined(KINETIS_CLKDIV1_OUTDIV2) || defined(__DOXYGEN__)
116 #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
117 #define KINETIS_CLKDIV1_OUTDIV2 (KINETIS_PLLCLK_FREQUENCY/KINETIS_BUSCLK_FREQUENCY)
118 #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
119 #define KINETIS_CLKDIV1_OUTDIV2 KINETIS_CLKDIV1_OUTDIV1
120 #else
121 #define KINETIS_CLKDIV1_OUTDIV2 2
122 #endif
123#endif
124
125/**
126 * @brief Clock divider for flash clock (OUTDIV4).
127 * @note The allowed range is 1..16
128 * @note The default value is calculated for a 24 MHz flash clock
129 * from a 96 MHz PLL output
130 */
131#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
132 #if defined(KINETIS_FLASHCLK_FREQUENCY) && KINETIS_FLASHCLK_FREQUENCY > 0
133 #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLASHCLK_FREQUENCY)
134 #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
135 #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_CLKDIV1_OUTDIV1*2)
136 #else
137 #define KINETIS_CLKDIV1_OUTDIV4 4
138 #endif
139#endif
140
141/**
142 * @brief FLL DCO tuning enable for 32.768 kHz reference.
143 * @note Set to 1 for fine-tuning DCO for maximum frequency with
144 * a 32.768 kHz reference.
145 * @note The default value is for a 32.768 kHz external crystal.
146 */
147#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
148#define KINETIS_MCG_FLL_DMX32 1
149#endif
150
151/**
152 * @brief FLL DCO range selection.
153 * @note The allowed range is 0...3.
154 * @note The default value is calculated for 48 MHz FLL output
155 * from a 32.768 kHz external crystal.
156 * (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
157 *
158 */
159#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
160#define KINETIS_MCG_FLL_DRS 2
161#endif
162
163/**
164 * @brief MCU system/core clock frequency.
165 */
166#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
167#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
168#endif
169
170/**
171 * @brief MCU bus clock frequency.
172 */
173#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
174#define KINETIS_BUSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV2)
175#endif
176
177/**
178 * @brief MCU flash clock frequency.
179 */
180#if !defined(KINETIS_FLASHCLK_FREQUENCY) || defined(__DOXYGEN__)
181#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
182#endif
183
184/**
185 * FTM clock frequency
186 */
187#if !defined(KINETIS_FTM_FREQUENCY) || defined(__DOXYGEN__)
188#define KINETIS_FTM_FREQUENCY KINETIS_SYSCLK_FREQUENCY
189#endif
190
191/** @} */
192
193/*===========================================================================*/
194/* Derived constants and error checks. */
195/*===========================================================================*/
196
197#if !defined(KINETIS_SYSCLK_FREQUENCY)
198 #error KINETIS_SYSCLK_FREQUENCY must be defined
199#endif
200
201#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
202 #error KINETIS_SYSCLK_FREQUENCY out of range
203#endif
204
205#if !defined(KINETIS_BUSCLK_FREQUENCY)
206 #error KINETIS_BUSCLK_FREQUENCY must be defined
207#endif
208
209#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
210 #error KINETIS_BUSCLK_FREQUENCY out of range
211#endif
212
213#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
214 #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
215 KINETIS_SYSCLK_FREQUENCY
216#endif
217
218#if !defined(KINETIS_FLASHCLK_FREQUENCY)
219 #error KINETIS_FLASHCLK_FREQUENCY must be defined
220#endif
221
222#if KINETIS_FLASHCLK_FREQUENCY <= 0 || KINETIS_FLASHCLK_FREQUENCY > KINETIS_FLASHCLK_MAX
223 #error KINETIS_FLASHCLK_FREQUENCY out of range
224#endif
225
226#if KINETIS_FLASHCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
227 #error KINETIS_FLASHCLK_FREQUENCY must be an integer divide of\
228 KINETIS_SYSCLK_FREQUENCY
229#endif
230
231#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
232 KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
233 #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
234#endif
235
236#if !(defined(KINETIS_CLKDIV1_OUTDIV2) && \
237 KINETIS_CLKDIV1_OUTDIV2 >= 1 && KINETIS_CLKDIV1_OUTDIV2 <= 16)
238#error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16
239#endif
240
241#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
242 KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
243#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
244#endif
245
246#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
247#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
248#endif
249
250#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
251#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
252#endif
253
254// This is needed by FlexNVM driver?
255//#define FTFx_DRIVER_IS_FLASH_RESIDENT 1
256
257/*===========================================================================*/
258/* Driver data structures and types. */
259/*===========================================================================*/
260
261/**
262 * @brief Type representing a system clock frequency.
263 */
264typedef uint32_t halclock_t;
265
266/**
267 * @brief Type of the realtime free counter value.
268 */
269typedef uint32_t halrtcnt_t;
270
271/*===========================================================================*/
272/* Driver macros. */
273/*===========================================================================*/
274
275/**
276 * @brief Returns the current value of the system free running counter.
277 * @note This service is implemented by returning the content of the
278 * DWT_CYCCNT register.
279 *
280 * @return The value of the system free running counter of
281 * type halrtcnt_t.
282 *
283 * @notapi
284 */
285#define hal_lld_get_counter_value() 0
286
287/**
288 * @brief Realtime counter frequency.
289 * @note The DWT_CYCCNT register is incremented directly by the system
290 * clock so this function returns STM32_HCLK.
291 *
292 * @return The realtime counter frequency of type halclock_t.
293 *
294 * @notapi
295 */
296#define hal_lld_get_counter_frequency() 0
297
298/*===========================================================================*/
299/* External declarations. */
300/*===========================================================================*/
301
302#include "nvic.h"
303
304#ifdef __cplusplus
305extern "C" {
306#endif
307 void hal_lld_init(void);
308 void ke1xf_init(void);
309#ifdef __cplusplus
310}
311#endif
312
313#endif /* HAL_LLD_H_ */
314
315/** @} */
hal_lld_init
void hal_lld_init(void)
Low level HAL driver initialization.
Definition hal_lld.c:97
ke1xf_init
void ke1xf_init(void)
KE1xF initialization.
Definition hal_lld.c:112
halrtcnt_t
uint32_t halrtcnt_t
Type of the realtime free counter value.
Definition hal_lld.h:269
halclock_t
uint32_t halclock_t
Type representing a system clock frequency.
Definition hal_lld.h:264
kinetis_dma.h
kinetis_registry.h
KE1xF capabilities registry.
kinetis_stm32.h
This is needed for better compatibility with STM32 or other CPUs of Kinetis family.
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