Lpspi_driver

Data Structures
struct	_lpspi_master_config
	LPSPI master configuration structure. More...
struct	_lpspi_slave_config
	LPSPI slave configuration structure. More...
struct	_lpspi_transfer
	LPSPI master/slave transfer structure. More...
struct	_lpspi_master_handle
	LPSPI master transfer handle structure used for transactional API. More...
struct	_lpspi_slave_handle
	LPSPI slave transfer handle structure used for transactional API. More...

Driver version
enum	_lpspi_status { kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0) , kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1) , kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2) , kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3) }
	Status for the LPSPI driver. More...
enum	_lpspi_flags {   kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK , kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK , kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK , kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK ,   kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK , kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK , kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK , kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK ,   kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK , kLPSPI_AllStatusFlag }
	LPSPI status flags in SPIx_SR register. More...
enum	_lpspi_interrupt_enable {   kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK , kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK , kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK , kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK ,   kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK , kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK , kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK , kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK ,   kLPSPI_AllInterruptEnable }
	LPSPI interrupt source. More...
enum	_lpspi_dma_enable { kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK , kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK }
	LPSPI DMA source. More...
enum	_lpspi_master_slave_mode { kLPSPI_Master = 1U , kLPSPI_Slave = 0U }
	LPSPI master or slave mode configuration. More...
enum	_lpspi_which_pcs_config { kLPSPI_Pcs0 = 0U , kLPSPI_Pcs1 = 1U , kLPSPI_Pcs2 = 2U , kLPSPI_Pcs3 = 3U }
	LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure). More...
enum	_lpspi_pcs_polarity_config { kLPSPI_PcsActiveHigh = 1U , kLPSPI_PcsActiveLow = 0U }
	LPSPI Peripheral Chip Select (PCS) Polarity configuration. More...
enum	_lpspi_pcs_polarity {   kLPSPI_Pcs0ActiveLow = 1U << 0 , kLPSPI_Pcs1ActiveLow = 1U << 1 , kLPSPI_Pcs2ActiveLow = 1U << 2 , kLPSPI_Pcs3ActiveLow = 1U << 3 ,   kLPSPI_PcsAllActiveLow = 0xFU }
	LPSPI Peripheral Chip Select (PCS) Polarity. More...
enum	_lpspi_clock_polarity { kLPSPI_ClockPolarityActiveHigh = 0U , kLPSPI_ClockPolarityActiveLow = 1U }
	LPSPI clock polarity configuration. More...
enum	_lpspi_clock_phase { kLPSPI_ClockPhaseFirstEdge = 0U , kLPSPI_ClockPhaseSecondEdge = 1U }
	LPSPI clock phase configuration. More...
enum	_lpspi_shift_direction { kLPSPI_MsbFirst = 0U , kLPSPI_LsbFirst = 1U }
	LPSPI data shifter direction options. More...
enum	_lpspi_host_request_select { kLPSPI_HostReqExtPin = 0U , kLPSPI_HostReqInternalTrigger = 1U }
	LPSPI Host Request select configuration. More...
enum	_lpspi_match_config {   kLPSI_MatchDisabled = 0x0U , kLPSI_1stWordEqualsM0orM1 = 0x2U , kLPSI_AnyWordEqualsM0orM1 = 0x3U , kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U ,   kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U , kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U , kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U }
	LPSPI Match configuration options. More...
enum	_lpspi_pin_config { kLPSPI_SdiInSdoOut = 0U , kLPSPI_SdiInSdiOut = 1U , kLPSPI_SdoInSdoOut = 2U , kLPSPI_SdoInSdiOut = 3U }
	LPSPI pin (SDO and SDI) configuration. More...
enum	_lpspi_data_out_config { kLpspiDataOutRetained = 0U , kLpspiDataOutTristate = 1U }
	LPSPI data output configuration. More...
enum	_lpspi_transfer_width { kLPSPI_SingleBitXfer = 0U , kLPSPI_TwoBitXfer = 1U , kLPSPI_FourBitXfer = 2U }
	LPSPI transfer width configuration. More...
enum	_lpspi_delay_type { kLPSPI_PcsToSck = 1U , kLPSPI_LastSckToPcs , kLPSPI_BetweenTransfer }
	LPSPI delay type selection. More...
enum	_lpspi_transfer_config_flag_for_master {   kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT , kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT , kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT , kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT ,   kLPSPI_MasterPcsContinuous = 1U << 20 , kLPSPI_MasterByteSwap }
	Use this enumeration for LPSPI master transfer configFlags. More...
enum	_lpspi_transfer_config_flag_for_slave {   kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT , kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT , kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT , kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT ,   kLPSPI_SlaveByteSwap }
	Use this enumeration for LPSPI slave transfer configFlags. More...
enum	_lpspi_transfer_state { kLPSPI_Idle = 0x0U , kLPSPI_Busy , kLPSPI_Error }
	LPSPI transfer state, which is used for LPSPI transactional API state machine. More...
typedef enum _lpspi_master_slave_mode	lpspi_master_slave_mode_t
	LPSPI master or slave mode configuration.
typedef enum _lpspi_which_pcs_config	lpspi_which_pcs_t
	LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).
typedef enum _lpspi_pcs_polarity_config	lpspi_pcs_polarity_config_t
	LPSPI Peripheral Chip Select (PCS) Polarity configuration.
typedef enum _lpspi_clock_polarity	lpspi_clock_polarity_t
	LPSPI clock polarity configuration.
typedef enum _lpspi_clock_phase	lpspi_clock_phase_t
	LPSPI clock phase configuration.
typedef enum _lpspi_shift_direction	lpspi_shift_direction_t
	LPSPI data shifter direction options.
typedef enum _lpspi_host_request_select	lpspi_host_request_select_t
	LPSPI Host Request select configuration.
typedef enum _lpspi_match_config	lpspi_match_config_t
	LPSPI Match configuration options.
typedef enum _lpspi_pin_config	lpspi_pin_config_t
	LPSPI pin (SDO and SDI) configuration.
typedef enum _lpspi_data_out_config	lpspi_data_out_config_t
	LPSPI data output configuration.
typedef enum _lpspi_transfer_width	lpspi_transfer_width_t
	LPSPI transfer width configuration.
typedef enum _lpspi_delay_type	lpspi_delay_type_t
	LPSPI delay type selection.
typedef struct _lpspi_master_config	lpspi_master_config_t
	LPSPI master configuration structure.
typedef struct _lpspi_slave_config	lpspi_slave_config_t
	LPSPI slave configuration structure.
typedef struct _lpspi_master_handle	lpspi_master_handle_t
	Forward declaration of the _lpspi_master_handle typedefs.
typedef struct _lpspi_slave_handle	lpspi_slave_handle_t
	Forward declaration of the _lpspi_slave_handle typedefs.
typedef void(*	lpspi_master_transfer_callback_t) (LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData)
	Master completion callback function pointer type.
typedef void(*	lpspi_slave_transfer_callback_t) (LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData)
	Slave completion callback function pointer type.
typedef struct _lpspi_transfer	lpspi_transfer_t
	LPSPI master/slave transfer structure.
volatile uint8_t	g_lpspiDummyData []
	Global variable for dummy data value setting.

Initialization and deinitialization
void	LPSPI_MasterInit (LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
	Initializes the LPSPI master.
void	LPSPI_MasterGetDefaultConfig (lpspi_master_config_t *masterConfig)
	Sets the lpspi_master_config_t structure to default values.
void	LPSPI_SlaveInit (LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)
	LPSPI slave configuration.
void	LPSPI_SlaveGetDefaultConfig (lpspi_slave_config_t *slaveConfig)
	Sets the lpspi_slave_config_t structure to default values.
void	LPSPI_Deinit (LPSPI_Type *base)
	De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock.
void	LPSPI_Reset (LPSPI_Type *base)
	Restores the LPSPI peripheral to reset state. Note that this function sets all registers to reset state. As a result, the LPSPI module can't work after calling this API.
static void	LPSPI_Enable (LPSPI_Type *base, bool enable)
	Enables the LPSPI peripheral and sets the MCR MDIS to 0.

Status
static uint32_t	LPSPI_GetStatusFlags (LPSPI_Type *base)
	Gets the LPSPI status flag state.
static uint32_t	LPSPI_GetTxFifoSize (LPSPI_Type *base)
	Gets the LPSPI Tx FIFO size.
static uint32_t	LPSPI_GetRxFifoSize (LPSPI_Type *base)
	Gets the LPSPI Rx FIFO size.
static uint32_t	LPSPI_GetTxFifoCount (LPSPI_Type *base)
	Gets the LPSPI Tx FIFO count.
static uint32_t	LPSPI_GetRxFifoCount (LPSPI_Type *base)
	Gets the LPSPI Rx FIFO count.
static void	LPSPI_ClearStatusFlags (LPSPI_Type *base, uint32_t statusFlags)
	Clears the LPSPI status flag.

Interrupts
static void	LPSPI_EnableInterrupts (LPSPI_Type *base, uint32_t mask)
	Enables the LPSPI interrupts.
static void	LPSPI_DisableInterrupts (LPSPI_Type *base, uint32_t mask)
	Disables the LPSPI interrupts.

DMA Control
static void	LPSPI_EnableDMA (LPSPI_Type *base, uint32_t mask)
	Enables the LPSPI DMA request.
static void	LPSPI_DisableDMA (LPSPI_Type *base, uint32_t mask)
	Disables the LPSPI DMA request.
static uint32_t	LPSPI_GetTxRegisterAddress (LPSPI_Type *base)
	Gets the LPSPI Transmit Data Register address for a DMA operation.
static uint32_t	LPSPI_GetRxRegisterAddress (LPSPI_Type *base)
	Gets the LPSPI Receive Data Register address for a DMA operation.

Bus Operations
bool	LPSPI_CheckTransferArgument (lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame)
	Check the argument for transfer .
static void	LPSPI_SetMasterSlaveMode (LPSPI_Type *base, lpspi_master_slave_mode_t mode)
	Configures the LPSPI for either master or slave.
static bool	LPSPI_IsMaster (LPSPI_Type *base)
	Returns whether the LPSPI module is in master mode.
static void	LPSPI_FlushFifo (LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)
	Flushes the LPSPI FIFOs.
static void	LPSPI_SetFifoWatermarks (LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)
	Sets the transmit and receive FIFO watermark values.
static void	LPSPI_SetAllPcsPolarity (LPSPI_Type *base, uint32_t mask)
	Configures all LPSPI peripheral chip select polarities simultaneously.
static void	LPSPI_SetFrameSize (LPSPI_Type *base, uint32_t frameSize)
	Configures the frame size.
uint32_t	LPSPI_MasterSetBaudRate (LPSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz, uint32_t *tcrPrescaleValue)
	Sets the LPSPI baud rate in bits per second.
void	LPSPI_MasterSetDelayScaler (LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay)
	Manually configures a specific LPSPI delay parameter (module must be disabled to change the delay values).
uint32_t	LPSPI_MasterSetDelayTimes (LPSPI_Type *base, uint32_t delayTimeInNanoSec, lpspi_delay_type_t whichDelay, uint32_t srcClock_Hz)
	Calculates the delay based on the desired delay input in nanoseconds (module must be disabled to change the delay values).
static void	LPSPI_WriteData (LPSPI_Type *base, uint32_t data)
	Writes data into the transmit data buffer.
static uint32_t	LPSPI_ReadData (LPSPI_Type *base)
	Reads data from the data buffer.
void	LPSPI_SetDummyData (LPSPI_Type *base, uint8_t dummyData)
	Set up the dummy data.

Transactional
void	LPSPI_MasterTransferCreateHandle (LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_master_transfer_callback_t callback, void *userData)
	Initializes the LPSPI master handle.
status_t	LPSPI_MasterTransferBlocking (LPSPI_Type *base, lpspi_transfer_t *transfer)
	LPSPI master transfer data using a polling method.
status_t	LPSPI_MasterTransferNonBlocking (LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer)
	LPSPI master transfer data using an interrupt method.
status_t	LPSPI_MasterTransferGetCount (LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count)
	Gets the master transfer remaining bytes.
void	LPSPI_MasterTransferAbort (LPSPI_Type *base, lpspi_master_handle_t *handle)
	LPSPI master abort transfer which uses an interrupt method.
void	LPSPI_MasterTransferHandleIRQ (LPSPI_Type *base, lpspi_master_handle_t *handle)
	LPSPI Master IRQ handler function.
void	LPSPI_SlaveTransferCreateHandle (LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_slave_transfer_callback_t callback, void *userData)
	Initializes the LPSPI slave handle.
status_t	LPSPI_SlaveTransferNonBlocking (LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer)
	LPSPI slave transfer data using an interrupt method.
status_t	LPSPI_SlaveTransferGetCount (LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count)
	Gets the slave transfer remaining bytes.
void	LPSPI_SlaveTransferAbort (LPSPI_Type *base, lpspi_slave_handle_t *handle)
	LPSPI slave aborts a transfer which uses an interrupt method.
void	LPSPI_SlaveTransferHandleIRQ (LPSPI_Type *base, lpspi_slave_handle_t *handle)
	LPSPI Slave IRQ handler function.

Detailed Description

Typedef Documentation

lpspi_clock_phase_t

typedef enum _lpspi_clock_phase lpspi_clock_phase_t

LPSPI clock phase configuration.

lpspi_clock_polarity_t

typedef enum _lpspi_clock_polarity lpspi_clock_polarity_t

LPSPI clock polarity configuration.

lpspi_data_out_config_t

typedef enum _lpspi_data_out_config lpspi_data_out_config_t

LPSPI data output configuration.

lpspi_delay_type_t

typedef enum _lpspi_delay_type lpspi_delay_type_t

LPSPI delay type selection.

lpspi_host_request_select_t

typedef enum _lpspi_host_request_select lpspi_host_request_select_t

LPSPI Host Request select configuration.

lpspi_master_config_t

typedef struct _lpspi_master_config lpspi_master_config_t

LPSPI master configuration structure.

lpspi_master_handle_t

typedef struct _lpspi_master_handle lpspi_master_handle_t

Forward declaration of the _lpspi_master_handle typedefs.

Definition at line 302 of file fsl_lpspi.h.

lpspi_master_slave_mode_t

typedef enum _lpspi_master_slave_mode lpspi_master_slave_mode_t

LPSPI master or slave mode configuration.

lpspi_master_transfer_callback_t

typedef void(* lpspi_master_transfer_callback_t) (LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData)

Master completion callback function pointer type.

Parameters

base	LPSPI peripheral address.
handle	Pointer to the handle for the LPSPI master.
status	Success or error code describing whether the transfer is completed.
userData	Arbitrary pointer-dataSized value passed from the application.

Definition at line 317 of file fsl_lpspi.h.

lpspi_match_config_t

typedef enum _lpspi_match_config lpspi_match_config_t

LPSPI Match configuration options.

lpspi_pcs_polarity_config_t

typedef enum _lpspi_pcs_polarity_config lpspi_pcs_polarity_config_t

LPSPI Peripheral Chip Select (PCS) Polarity configuration.

lpspi_pin_config_t

typedef enum _lpspi_pin_config lpspi_pin_config_t

LPSPI pin (SDO and SDI) configuration.

lpspi_shift_direction_t

typedef enum _lpspi_shift_direction lpspi_shift_direction_t

LPSPI data shifter direction options.

lpspi_slave_config_t

typedef struct _lpspi_slave_config lpspi_slave_config_t

LPSPI slave configuration structure.

lpspi_slave_handle_t

typedef struct _lpspi_slave_handle lpspi_slave_handle_t

Forward declaration of the _lpspi_slave_handle typedefs.

Definition at line 307 of file fsl_lpspi.h.

lpspi_slave_transfer_callback_t

typedef void(* lpspi_slave_transfer_callback_t) (LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData)

Slave completion callback function pointer type.

Parameters

base	LPSPI peripheral address.
handle	Pointer to the handle for the LPSPI slave.
status	Success or error code describing whether the transfer is completed.
userData	Arbitrary pointer-dataSized value passed from the application.

Definition at line 330 of file fsl_lpspi.h.

lpspi_transfer_t

typedef struct _lpspi_transfer lpspi_transfer_t

LPSPI master/slave transfer structure.

lpspi_transfer_width_t

typedef enum _lpspi_transfer_width lpspi_transfer_width_t

LPSPI transfer width configuration.

lpspi_which_pcs_t

typedef enum _lpspi_which_pcs_config lpspi_which_pcs_t

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).

Enumeration Type Documentation

_lpspi_clock_phase

enum _lpspi_clock_phase

LPSPI clock phase configuration.

Enumerator
kLPSPI_ClockPhaseFirstEdge	CPHA=0. Data is captured on the leading edge of the SCK and changed on the following edge.
kLPSPI_ClockPhaseSecondEdge	CPHA=1. Data is changed on the leading edge of the SCK and captured on the following edge.

Definition at line 126 of file fsl_lpspi.h.

{
    kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the
                                         following edge.*/
    kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the
                                        following edge.*/
} lpspi_clock_phase_t;

_lpspi_clock_polarity

enum _lpspi_clock_polarity

LPSPI clock polarity configuration.

Enumerator
kLPSPI_ClockPolarityActiveHigh	CPOL=0. Active-high LPSPI clock (idles low)
kLPSPI_ClockPolarityActiveLow	CPOL=1. Active-low LPSPI clock (idles high)

Definition at line 119 of file fsl_lpspi.h.

{
    kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/
    kLPSPI_ClockPolarityActiveLow = 1U   /*!< CPOL=1. Active-low LPSPI clock (idles high)*/
} lpspi_clock_polarity_t;

_lpspi_data_out_config

enum _lpspi_data_out_config

LPSPI data output configuration.

Enumerator
kLpspiDataOutRetained	Data out retains last value when chip select is de-asserted
kLpspiDataOutTristate	Data out is tristated when chip select is de-asserted

Definition at line 170 of file fsl_lpspi.h.

{
    kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */
    kLpspiDataOutTristate = 1U  /*!< Data out is tristated when chip select is de-asserted */
} lpspi_data_out_config_t;

_lpspi_delay_type

enum _lpspi_delay_type

LPSPI delay type selection.

Enumerator
kLPSPI_PcsToSck	PCS-to-SCK delay.
kLPSPI_LastSckToPcs	Last SCK edge to PCS delay.
kLPSPI_BetweenTransfer	Delay between transfers.

Definition at line 185 of file fsl_lpspi.h.

{
    kLPSPI_PcsToSck = 1U,  /*!< PCS-to-SCK delay. */
    kLPSPI_LastSckToPcs,   /*!< Last SCK edge to PCS delay. */
    kLPSPI_BetweenTransfer /*!< Delay between transfers. */
} lpspi_delay_type_t;

_lpspi_dma_enable

enum _lpspi_dma_enable

LPSPI DMA source.

Enumerator
kLPSPI_TxDmaEnable	Transmit data DMA enable
kLPSPI_RxDmaEnable	Receive data DMA enable

Definition at line 79 of file fsl_lpspi.h.

{
    kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */
    kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK  /*!< Receive data DMA enable */
};

_lpspi_flags

enum _lpspi_flags

LPSPI status flags in SPIx_SR register.

Enumerator
kLPSPI_TxDataRequestFlag	Transmit data flag
kLPSPI_RxDataReadyFlag	Receive data flag
kLPSPI_WordCompleteFlag	Word Complete flag
kLPSPI_FrameCompleteFlag	Frame Complete flag
kLPSPI_TransferCompleteFlag	Transfer Complete flag
kLPSPI_TransmitErrorFlag	Transmit Error flag (FIFO underrun)
kLPSPI_ReceiveErrorFlag	Receive Error flag (FIFO overrun)
kLPSPI_DataMatchFlag	Data Match flag
kLPSPI_ModuleBusyFlag	Module Busy flag
kLPSPI_AllStatusFlag	Used for clearing all w1c status flags

Definition at line 46 of file fsl_lpspi.h.

{
    kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK,    /*!< Transmit data flag */
    kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK,      /*!< Receive data flag */
    kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK,     /*!< Word Complete flag */
    kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK,    /*!< Frame Complete flag */
    kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */
    kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK,    /*!< Transmit Error flag (FIFO underrun) */
    kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK,     /*!< Receive Error flag (FIFO overrun) */
    kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK,        /*!< Data Match flag */
    kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK,       /*!< Module Busy flag */
    kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK |
                            LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK |
                            LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */
};

_lpspi_host_request_select

enum _lpspi_host_request_select

LPSPI Host Request select configuration.

Enumerator
kLPSPI_HostReqExtPin	Host Request is an ext pin.
kLPSPI_HostReqInternalTrigger	Host Request is an internal trigger.

Definition at line 142 of file fsl_lpspi.h.

{
    kLPSPI_HostReqExtPin = 0U,         /*!< Host Request is an ext pin. */
    kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */
} lpspi_host_request_select_t;

_lpspi_interrupt_enable

enum _lpspi_interrupt_enable

LPSPI interrupt source.

Enumerator
kLPSPI_TxInterruptEnable	Transmit data interrupt enable
kLPSPI_RxInterruptEnable	Receive data interrupt enable
kLPSPI_WordCompleteInterruptEnable	Word complete interrupt enable
kLPSPI_FrameCompleteInterruptEnable	Frame complete interrupt enable
kLPSPI_TransferCompleteInterruptEnable	Transfer complete interrupt enable
kLPSPI_TransmitErrorInterruptEnable	Transmit error interrupt enable(FIFO underrun)
kLPSPI_ReceiveErrorInterruptEnable	Receive Error interrupt enable (FIFO overrun)
kLPSPI_DataMatchInterruptEnable	Data Match interrupt enable
kLPSPI_AllInterruptEnable	All above interrupts enable.

Definition at line 63 of file fsl_lpspi.h.

{
    kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK,               /*!< Transmit data interrupt enable */
    kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK,               /*!< Receive data interrupt enable */
    kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK,     /*!< Word complete interrupt enable */
    kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK,    /*!< Frame complete interrupt enable */
    kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */
    kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK,    /*!< Transmit error interrupt enable(FIFO underrun)*/
    kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK,     /*!< Receive Error interrupt enable (FIFO overrun) */
    kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK,        /*!< Data Match interrupt enable */
    kLPSPI_AllInterruptEnable =
        (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK |
         LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/
};

_lpspi_master_slave_mode

enum _lpspi_master_slave_mode

LPSPI master or slave mode configuration.

Enumerator
kLPSPI_Master	LPSPI peripheral operates in master mode.
kLPSPI_Slave	LPSPI peripheral operates in slave mode.

Definition at line 86 of file fsl_lpspi.h.

{
    kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/
    kLPSPI_Slave = 0U   /*!< LPSPI peripheral operates in slave mode.*/
} lpspi_master_slave_mode_t;

_lpspi_match_config

enum _lpspi_match_config

LPSPI Match configuration options.

Enumerator
kLPSI_MatchDisabled	LPSPI Match Disabled.
kLPSI_1stWordEqualsM0orM1	LPSPI Match Enabled.
kLPSI_AnyWordEqualsM0orM1	LPSPI Match Enabled.
kLPSI_1stWordEqualsM0and2ndWordEqualsM1	LPSPI Match Enabled.
kLPSI_AnyWordEqualsM0andNxtWordEqualsM1	LPSPI Match Enabled.
kLPSI_1stWordAndM1EqualsM0andM1	LPSPI Match Enabled.
kLPSI_AnyWordAndM1EqualsM0andM1	LPSPI Match Enabled.

Definition at line 149 of file fsl_lpspi.h.

{
    kLPSI_MatchDisabled = 0x0U,                     /*!< LPSPI Match Disabled. */
    kLPSI_1stWordEqualsM0orM1 = 0x2U,               /*!< LPSPI Match Enabled. */
    kLPSI_AnyWordEqualsM0orM1 = 0x3U,               /*!< LPSPI Match Enabled. */
    kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */
    kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */
    kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U,         /*!< LPSPI Match Enabled. */
    kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U,         /*!< LPSPI Match Enabled. */
} lpspi_match_config_t;

_lpspi_pcs_polarity

enum _lpspi_pcs_polarity

LPSPI Peripheral Chip Select (PCS) Polarity.

Enumerator
kLPSPI_Pcs0ActiveLow	Pcs0 Active Low (idles high).
kLPSPI_Pcs1ActiveLow	Pcs1 Active Low (idles high).
kLPSPI_Pcs2ActiveLow	Pcs2 Active Low (idles high).
kLPSPI_Pcs3ActiveLow	Pcs3 Active Low (idles high).
kLPSPI_PcsAllActiveLow	Pcs0 to Pcs5 Active Low (idles high).

Definition at line 109 of file fsl_lpspi.h.

{
    kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */
    kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */
    kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */
    kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */
    kLPSPI_PcsAllActiveLow = 0xFU   /*!< Pcs0 to Pcs5 Active Low (idles high). */
};

_lpspi_pcs_polarity_config

enum _lpspi_pcs_polarity_config

LPSPI Peripheral Chip Select (PCS) Polarity configuration.

Enumerator
kLPSPI_PcsActiveHigh	PCS Active High (idles low)
kLPSPI_PcsActiveLow	PCS Active Low (idles high)

Definition at line 102 of file fsl_lpspi.h.

{
    kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */
    kLPSPI_PcsActiveLow = 0U   /*!< PCS Active Low (idles high) */
} lpspi_pcs_polarity_config_t;

_lpspi_pin_config

enum _lpspi_pin_config

LPSPI pin (SDO and SDI) configuration.

Enumerator
kLPSPI_SdiInSdoOut	LPSPI SDI input, SDO output.
kLPSPI_SdiInSdiOut	LPSPI SDI input, SDI output.
kLPSPI_SdoInSdoOut	LPSPI SDO input, SDO output.
kLPSPI_SdoInSdiOut	LPSPI SDO input, SDI output.

Definition at line 161 of file fsl_lpspi.h.

{
    kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */
    kLPSPI_SdiInSdiOut = 1U, /*!< LPSPI SDI input, SDI output. */
    kLPSPI_SdoInSdoOut = 2U, /*!< LPSPI SDO input, SDO output. */
    kLPSPI_SdoInSdiOut = 3U  /*!< LPSPI SDO input, SDI output. */
} lpspi_pin_config_t;

_lpspi_shift_direction

enum _lpspi_shift_direction

LPSPI data shifter direction options.

Enumerator
kLPSPI_MsbFirst	Data transfers start with most significant bit.
kLPSPI_LsbFirst	Data transfers start with least significant bit.

Definition at line 135 of file fsl_lpspi.h.

{
    kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/
    kLPSPI_LsbFirst = 1U  /*!< Data transfers start with least significant bit.*/
} lpspi_shift_direction_t;

_lpspi_status

enum _lpspi_status

Status for the LPSPI driver.

Enumerator
kStatus_LPSPI_Busy	LPSPI transfer is busy.
kStatus_LPSPI_Error	LPSPI driver error.
kStatus_LPSPI_Idle	LPSPI is idle.
kStatus_LPSPI_OutOfRange	LPSPI transfer out Of range.

Definition at line 37 of file fsl_lpspi.h.

{
    kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0),      /*!< LPSPI transfer is busy.*/
    kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1),     /*!< LPSPI driver error. */
    kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2),      /*!< LPSPI is idle.*/
    kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3) /*!< LPSPI transfer out Of range. */
};

_lpspi_transfer_config_flag_for_master

enum _lpspi_transfer_config_flag_for_master

Use this enumeration for LPSPI master transfer configFlags.

Enumerator
kLPSPI_MasterPcs0	LPSPI master transfer use PCS0 signal
kLPSPI_MasterPcs1	LPSPI master transfer use PCS1 signal
kLPSPI_MasterPcs2	LPSPI master transfer use PCS2 signal
kLPSPI_MasterPcs3	LPSPI master transfer use PCS3 signal
kLPSPI_MasterPcsContinuous	Is PCS signal continuous
kLPSPI_MasterByteSwap	Is master swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB). If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used or not, the waveform is 1 2 3 4 5 6 7 8. If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.

Definition at line 196 of file fsl_lpspi.h.

{
    kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */
    kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */
    kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */
    kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */
 
    kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */
 
    kLPSPI_MasterByteSwap =
        1U << 22 /*!< Is master swap the byte.
                       * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
                       * lpspi_shift_direction_t to MSB).
                       * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used
                       * or not, the waveform is 1 2 3 4 5 6 7 8.
                       * 2. If you set bitPerFrame = 16 :
                       * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag.
                       * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
                       * 3. If you set bitPerFrame = 32 :
                       * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag.
                       * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
                       */
};

_lpspi_transfer_config_flag_for_slave

enum _lpspi_transfer_config_flag_for_slave

Use this enumeration for LPSPI slave transfer configFlags.

Enumerator
kLPSPI_SlavePcs0	LPSPI slave transfer use PCS0 signal
kLPSPI_SlavePcs1	LPSPI slave transfer use PCS1 signal
kLPSPI_SlavePcs2	LPSPI slave transfer use PCS2 signal
kLPSPI_SlavePcs3	LPSPI slave transfer use PCS3 signal
kLPSPI_SlaveByteSwap	Is slave swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB). If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used or not, the waveform is 1 2 3 4 5 6 7 8. If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.

Definition at line 224 of file fsl_lpspi.h.

{
    kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */
    kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */
    kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */
    kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */
 
    kLPSPI_SlaveByteSwap =
        1U << 22 /*!< Is slave swap the byte.
                        * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
                        * lpspi_shift_direction_t to MSB).
                        * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used
                        * or not, the waveform is 1 2 3 4 5 6 7 8.
                        * 2. If you set bitPerFrame = 16 :
                        * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag.
                        * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
                        * 3. If you set bitPerFrame = 32 :
                        * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag.
                        * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
                        */
};

_lpspi_transfer_state

enum _lpspi_transfer_state

LPSPI transfer state, which is used for LPSPI transactional API state machine.

Enumerator
kLPSPI_Idle	Nothing in the transmitter/receiver.
kLPSPI_Busy	Transfer queue is not finished.
kLPSPI_Error	Transfer error.

Definition at line 247 of file fsl_lpspi.h.

{
    kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */
    kLPSPI_Busy,        /*!< Transfer queue is not finished. */
    kLPSPI_Error        /*!< Transfer error. */
};

_lpspi_transfer_width

enum _lpspi_transfer_width

LPSPI transfer width configuration.

Enumerator
kLPSPI_SingleBitXfer	1-bit shift at a time, data out on SDO, in on SDI (normal mode)
kLPSPI_TwoBitXfer	2-bits shift out on SDO/SDI and in on SDO/SDI
kLPSPI_FourBitXfer	4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2]

Definition at line 177 of file fsl_lpspi.h.

{
    kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */
    kLPSPI_TwoBitXfer = 1U,    /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */
    kLPSPI_FourBitXfer = 2U    /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */
} lpspi_transfer_width_t;

_lpspi_which_pcs_config

enum _lpspi_which_pcs_config

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).

Enumerator
kLPSPI_Pcs0	PCS[0]
kLPSPI_Pcs1	PCS[1]
kLPSPI_Pcs2	PCS[2]
kLPSPI_Pcs3	PCS[3]

Definition at line 93 of file fsl_lpspi.h.

{
    kLPSPI_Pcs0 = 0U, /*!< PCS[0] */
    kLPSPI_Pcs1 = 1U, /*!< PCS[1] */
    kLPSPI_Pcs2 = 2U, /*!< PCS[2] */
    kLPSPI_Pcs3 = 3U  /*!< PCS[3] */
} lpspi_which_pcs_t;

Function Documentation

LPSPI_CheckTransferArgument()

bool LPSPI_CheckTransferArgument	(	lpspi_transfer_t *	transfer,
		uint32_t	bitsPerFrame,
		uint32_t	bytesPerFrame
	)

Check the argument for transfer .

Parameters

transfer	the transfer struct to be used.
bitPerFrame	The bit size of one frame.
bytePerFrame	The byte size of one frame.

Returns

Return true for right and false for wrong.

brief Check the argument for transfer .

param transfer the transfer struct to be used. param bitPerFrame The bit size of one frame. param bytePerFrame The byte size of one frame. return Return true for right and false for wrong.

Definition at line 713 of file fsl_lpspi.c.

{
    assert(transfer);
 
    /* If the transfer count is zero, then return immediately.*/
    if (transfer->dataSize == 0)
    {
        return false;
    }
 
    /* If both send buffer and receive buffer is null */
    if ((!(transfer->txData)) && (!(transfer->rxData)))
    {
        return false;
    }
 
    /*The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4 .
     *For bytesPerFrame greater than 4 situation:
     *the transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4 ,
     *otherwise , the transfer data size can be integer multiples of bytesPerFrame.
     */
    if (bytesPerFrame <= 4)
    {
        if ((transfer->dataSize % bytesPerFrame) != 0)
        {
            return false;
        }
    }
    else
    {
        if ((bytesPerFrame % 4U) != 0)
        {
            if (transfer->dataSize != bytesPerFrame)
            {
                return false;
            }
        }
        else
        {
            if ((transfer->dataSize % bytesPerFrame) != 0)
            {
                return false;
            }
        }
    }
 
    return true;
}

Referenced by LPSPI_MasterTransferBlocking(), LPSPI_MasterTransferEDMA(), LPSPI_MasterTransferNonBlocking(), LPSPI_SlaveTransferEDMA(), and LPSPI_SlaveTransferNonBlocking().

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LPSPI_ClearStatusFlags()

static void LPSPI_ClearStatusFlags ( LPSPI_Type *  base, uint32_t  statusFlags  )

inlinestatic

Clears the LPSPI status flag.

This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. Example usage:

LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag);

Parameters

base	LPSPI peripheral address.
statusFlags	The status flag used from type _lpspi_flags.

< The status flags are cleared by writing 1 (w1c).

Definition at line 575 of file fsl_lpspi.h.

{
    base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/
}

Referenced by LPSPI_MasterTransferBlocking(), LPSPI_MasterTransferEDMA(), LPSPI_MasterTransferNonBlocking(), LPSPI_SlaveTransferEDMA(), LPSPI_SlaveTransferHandleIRQ(), and LPSPI_SlaveTransferNonBlocking().

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LPSPI_Deinit()

void LPSPI_Deinit

(

LPSPI_Type *

base

)

De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock.

Parameters

base	LPSPI peripheral address.

brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. param base LPSPI peripheral address.

Definition at line 367 of file fsl_lpspi.c.

{
    /* Reset to default value */
    LPSPI_Reset(base);
 
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 
    uint32_t instance = LPSPI_GetInstance(base);
    /* Enable LPSPI clock */
    CLOCK_DisableClock(s_lpspiClocks[instance]);
 
#if defined(LPSPI_PERIPH_CLOCKS)
    CLOCK_DisableClock(s_LpspiPeriphClocks[instance]);
#endif
 
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}

Referenced by spi_lld_stop().

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LPSPI_DisableDMA()

static void LPSPI_DisableDMA ( LPSPI_Type *  base, uint32_t  mask  )

inlinestatic

Disables the LPSPI DMA request.

This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.

SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);

Parameters

base	LPSPI peripheral address.
mask	The interrupt mask; Use the enum _lpspi_dma_enable.

Definition at line 658 of file fsl_lpspi.h.

{
    base->DER &= ~mask;
}

Referenced by EDMA_LpspiMasterCallback(), EDMA_LpspiSlaveCallback(), LPSPI_MasterTransferAbortEDMA(), LPSPI_MasterTransferEDMA(), LPSPI_SlaveTransferAbortEDMA(), and LPSPI_SlaveTransferEDMA().

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LPSPI_DisableInterrupts()

static void LPSPI_DisableInterrupts ( LPSPI_Type *  base, uint32_t  mask  )

inlinestatic

Disables the LPSPI interrupts.

LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );

Parameters

base	LPSPI peripheral address.
mask	The interrupt mask; Use the enum _lpspi_interrupt_enable.

Definition at line 617 of file fsl_lpspi.h.

{
    base->IER &= ~mask;
}

Referenced by LPSPI_MasterTransferAbort(), LPSPI_MasterTransferComplete(), LPSPI_MasterTransferEDMA(), LPSPI_MasterTransferHandleIRQ(), LPSPI_MasterTransferNonBlocking(), LPSPI_SlaveTransferAbort(), LPSPI_SlaveTransferComplete(), LPSPI_SlaveTransferEDMA(), LPSPI_SlaveTransferHandleIRQ(), and LPSPI_SlaveTransferNonBlocking().

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LPSPI_Enable()

static void LPSPI_Enable ( LPSPI_Type *  base, bool  enable  )

inlinestatic

Enables the LPSPI peripheral and sets the MCR MDIS to 0.

Parameters

base	LPSPI peripheral address.
enable	Pass true to enable module, false to disable module.

Definition at line 491 of file fsl_lpspi.h.

{
    if (enable)
    {
        base->CR |= LPSPI_CR_MEN_MASK;
    }
    else
    {
        base->CR &= ~LPSPI_CR_MEN_MASK;
    }
}

Referenced by LPSPI_MasterInit(), LPSPI_MasterTransferBlocking(), LPSPI_MasterTransferEDMA(), LPSPI_MasterTransferNonBlocking(), LPSPI_SlaveInit(), LPSPI_SlaveTransferEDMA(), and LPSPI_SlaveTransferNonBlocking().

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LPSPI_EnableDMA()

static void LPSPI_EnableDMA ( LPSPI_Type *  base, uint32_t  mask  )

inlinestatic

Enables the LPSPI DMA request.

This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.

LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);

Parameters

base	LPSPI peripheral address.
mask	The interrupt mask; Use the enum _lpspi_dma_enable.

Definition at line 642 of file fsl_lpspi.h.

{
    base->DER |= mask;
}

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

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LPSPI_EnableInterrupts()

static void LPSPI_EnableInterrupts ( LPSPI_Type *  base, uint32_t  mask  )

inlinestatic

Enables the LPSPI interrupts.

This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request.

LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );

Parameters

base	LPSPI peripheral address.
mask	The interrupt mask; Use the enum _lpspi_interrupt_enable.

Definition at line 602 of file fsl_lpspi.h.

{
    base->IER |= mask;
}

Referenced by LPSPI_MasterTransferHandleIRQ(), LPSPI_MasterTransferNonBlocking(), LPSPI_SlaveTransferHandleIRQ(), and LPSPI_SlaveTransferNonBlocking().

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LPSPI_FlushFifo()

static void LPSPI_FlushFifo ( LPSPI_Type *  base, bool  flushTxFifo, bool  flushRxFifo  )

inlinestatic

Flushes the LPSPI FIFOs.

Parameters

base	LPSPI peripheral address.
flushTxFifo	Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO.
flushRxFifo	Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO.

Definition at line 743 of file fsl_lpspi.h.

{
    base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT);
}

Referenced by LPSPI_MasterTransferBlocking(), LPSPI_MasterTransferEDMA(), LPSPI_MasterTransferNonBlocking(), LPSPI_SlaveTransferEDMA(), and LPSPI_SlaveTransferNonBlocking().

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LPSPI_GetRxFifoCount()

static uint32_t LPSPI_GetRxFifoCount ( LPSPI_Type *  base )

inlinestatic

Gets the LPSPI Rx FIFO count.

Parameters

base	LPSPI peripheral address.

Returns

The number of words in the receive FIFO.

Definition at line 557 of file fsl_lpspi.h.

{
    return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT);
}

Referenced by EDMA_LpspiMasterCallback(), EDMA_LpspiSlaveCallback(), LPSPI_MasterTransferBlocking(), LPSPI_MasterTransferHandleIRQ(), and LPSPI_SlaveTransferHandleIRQ().

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LPSPI_GetRxFifoSize()

static uint32_t LPSPI_GetRxFifoSize ( LPSPI_Type *  base )

inlinestatic

Gets the LPSPI Rx FIFO size.

Parameters

base	LPSPI peripheral address.

Returns

The LPSPI Rx FIFO size.

Definition at line 537 of file fsl_lpspi.h.

{
    return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT));
}

Referenced by LPSPI_MasterTransferBlocking(), LPSPI_MasterTransferEDMA(), LPSPI_MasterTransferNonBlocking(), LPSPI_SlaveTransferEDMA(), and LPSPI_SlaveTransferNonBlocking().

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LPSPI_GetRxRegisterAddress()

static uint32_t LPSPI_GetRxRegisterAddress ( LPSPI_Type *  base )

inlinestatic

Gets the LPSPI Receive Data Register address for a DMA operation.

This function gets the LPSPI Receive Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters

base	LPSPI peripheral address.

Returns

The LPSPI Receive Data Register address.

Definition at line 688 of file fsl_lpspi.h.

{
    return (uint32_t) & (base->RDR);
}

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

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LPSPI_GetStatusFlags()

static uint32_t LPSPI_GetStatusFlags ( LPSPI_Type *  base )

inlinestatic

Gets the LPSPI status flag state.

Parameters

base	LPSPI peripheral address.

Returns

The LPSPI status(in SR register).

Definition at line 517 of file fsl_lpspi.h.

{
    return (base->SR);
}

Referenced by LPSPI_MasterTransferBlocking(), LPSPI_MasterTransferHandleIRQ(), and LPSPI_SlaveTransferHandleIRQ().

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LPSPI_GetTxFifoCount()

static uint32_t LPSPI_GetTxFifoCount ( LPSPI_Type *  base )

inlinestatic

Gets the LPSPI Tx FIFO count.

Parameters

base	LPSPI peripheral address.

Returns

The number of words in the transmit FIFO.

Definition at line 547 of file fsl_lpspi.h.

{
    return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT);
}

Referenced by LPSPI_MasterTransferBlocking(), LPSPI_MasterTransferFillUpTxFifo(), LPSPI_MasterTransferHandleIRQ(), LPSPI_MasterTransferNonBlocking(), LPSPI_SlaveTransferFillUpTxFifo(), LPSPI_SlaveTransferHandleIRQ(), and LPSPI_SlaveTransferNonBlocking().

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LPSPI_GetTxFifoSize()

static uint32_t LPSPI_GetTxFifoSize ( LPSPI_Type *  base )

inlinestatic

Gets the LPSPI Tx FIFO size.

Parameters

base	LPSPI peripheral address.

Returns

The LPSPI Tx FIFO size.

Definition at line 527 of file fsl_lpspi.h.

{
    return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT));
}

LPSPI_GetTxRegisterAddress()

static uint32_t LPSPI_GetTxRegisterAddress ( LPSPI_Type *  base )

inlinestatic

Gets the LPSPI Transmit Data Register address for a DMA operation.

This function gets the LPSPI Transmit Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters

base	LPSPI peripheral address.

Returns

The LPSPI Transmit Data Register address.

Definition at line 673 of file fsl_lpspi.h.

{
    return (uint32_t) & (base->TDR);
}

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

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LPSPI_IsMaster()

static bool LPSPI_IsMaster ( LPSPI_Type *  base )

inlinestatic

Returns whether the LPSPI module is in master mode.

Parameters

base	LPSPI peripheral address.

Returns

Returns true if the module is in master mode or false if the module is in slave mode.

Definition at line 731 of file fsl_lpspi.h.

{
    return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK);
}

Referenced by LPSPI_CommonIRQHandler(), and LPSPI_MasterSetBaudRate().

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LPSPI_MasterGetDefaultConfig()

void LPSPI_MasterGetDefaultConfig

(

lpspi_master_config_t *

masterConfig

)

Sets the lpspi_master_config_t structure to default values.

This API initializes the configuration structure for LPSPI_MasterInit(). The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified before calling the LPSPI_MasterInit(). Example:

lpspi_master_config_t  masterConfig;
LPSPI_MasterGetDefaultConfig(&masterConfig);

Parameters

masterConfig

pointer to lpspi_master_config_t structure

brief Sets the lpspi_master_config_t structure to default values.

This API initializes the configuration structure for LPSPI_MasterInit(). The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified before calling the LPSPI_MasterInit(). Example: code lpspi_master_config_t masterConfig; LPSPI_MasterGetDefaultConfig(&masterConfig); endcode param masterConfig pointer to lpspi_master_config_t structure

Definition at line 249 of file fsl_lpspi.c.

{
    assert(masterConfig);
 
    /* Initializes the configure structure to zero. */
    memset(masterConfig, 0, sizeof(*masterConfig));
 
    masterConfig->baudRate = 500000;
    masterConfig->bitsPerFrame = 8;
    masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh;
    masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge;
    masterConfig->direction = kLPSPI_MsbFirst;
 
    masterConfig->pcsToSckDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2;
    masterConfig->lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2;
    masterConfig->betweenTransferDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2;
 
    masterConfig->whichPcs = kLPSPI_Pcs0;
    masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow;
 
    masterConfig->pinCfg = kLPSPI_SdiInSdoOut;
    masterConfig->dataOutConfig = kLpspiDataOutRetained;
}

Referenced by spi_lld_start().

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LPSPI_MasterInit()

void LPSPI_MasterInit	(	LPSPI_Type *	base,
		const lpspi_master_config_t *	masterConfig,
		uint32_t	srcClock_Hz
	)

Initializes the LPSPI master.

Parameters

base	LPSPI peripheral address.
masterConfig	Pointer to structure lpspi_master_config_t.
srcClock_Hz	Module source input clock in Hertz

brief Initializes the LPSPI master.

param base LPSPI peripheral address. param masterConfig Pointer to structure lpspi_master_config_t. param srcClock_Hz Module source input clock in Hertz

Definition at line 187 of file fsl_lpspi.c.

{
    assert(masterConfig);
 
    uint32_t tcrPrescaleValue = 0;
 
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 
    uint32_t instance = LPSPI_GetInstance(base);
    /* Enable LPSPI clock */
    CLOCK_EnableClock(s_lpspiClocks[instance]);
 
#if defined(LPSPI_PERIPH_CLOCKS)
    CLOCK_EnableClock(s_LpspiPeriphClocks[instance]);
#endif
 
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
    /* Set LPSPI to master */
    LPSPI_SetMasterSlaveMode(base, kLPSPI_Master);
 
    /* Set specific PCS to active high or low */
    LPSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow);
 
    /* Set Configuration Register 1 related setting.*/
    base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK)) |
                  LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) |
                  LPSPI_CFGR1_NOSTALL(0);
 
    /* Set baudrate and delay times*/
    LPSPI_MasterSetBaudRate(base, masterConfig->baudRate, srcClock_Hz, &tcrPrescaleValue);
 
    /* Set default watermarks */
    LPSPI_SetFifoWatermarks(base, kLpspiDefaultTxWatermark, kLpspiDefaultRxWatermark);
 
    /* Set Transmit Command Register*/
    base->TCR = LPSPI_TCR_CPOL(masterConfig->cpol) | LPSPI_TCR_CPHA(masterConfig->cpha) |
                LPSPI_TCR_LSBF(masterConfig->direction) | LPSPI_TCR_FRAMESZ(masterConfig->bitsPerFrame - 1) |
                LPSPI_TCR_PRESCALE(tcrPrescaleValue) | LPSPI_TCR_PCS(masterConfig->whichPcs);
 
    LPSPI_Enable(base, true);
 
    LPSPI_MasterSetDelayTimes(base, masterConfig->pcsToSckDelayInNanoSec, kLPSPI_PcsToSck, srcClock_Hz);
    LPSPI_MasterSetDelayTimes(base, masterConfig->lastSckToPcsDelayInNanoSec, kLPSPI_LastSckToPcs, srcClock_Hz);
    LPSPI_MasterSetDelayTimes(base, masterConfig->betweenTransferDelayInNanoSec, kLPSPI_BetweenTransfer, srcClock_Hz);
 
    LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA);
}

Referenced by spi_lld_start().

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LPSPI_MasterSetBaudRate()

uint32_t LPSPI_MasterSetBaudRate	(	LPSPI_Type *	base,
		uint32_t	baudRate_Bps,
		uint32_t	srcClock_Hz,
		uint32_t *	tcrPrescaleValue
	)

Sets the LPSPI baud rate in bits per second.

This function takes in the desired bitsPerSec (baud rate) and calculates the nearest possible baud rate without exceeding the desired baud rate and returns the calculated baud rate in bits-per-second. It requires the caller to provide the frequency of the module source clock (in Hertz). Note that the baud rate does not go into effect until the Transmit Control Register (TCR) is programmed with the prescale value. Hence, this function returns the prescale tcrPrescaleValue parameter for later programming in the TCR. The higher level peripheral driver should alert the user of an out of range baud rate input.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters

base	LPSPI peripheral address.
baudRate_Bps	The desired baud rate in bits per second.
srcClock_Hz	Module source input clock in Hertz.
tcrPrescaleValue	The TCR prescale value needed to program the TCR.

Returns

The actual calculated baud rate. This function may also return a "0" if the LPSPI is not configured for master mode or if the LPSPI module is not disabled.

brief Sets the LPSPI baud rate in bits per second.

This function takes in the desired bitsPerSec (baud rate) and calculates the nearest possible baud rate without exceeding the desired baud rate and returns the calculated baud rate in bits-per-second. It requires the caller to provide the frequency of the module source clock (in Hertz). Note that the baud rate does not go into effect until the Transmit Control Register (TCR) is programmed with the prescale value. Hence, this function returns the prescale tcrPrescaleValue parameter for later programming in the TCR. The higher level peripheral driver should alert the user of an out of range baud rate input.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

param base LPSPI peripheral address. param baudRate_Bps The desired baud rate in bits per second. param srcClock_Hz Module source input clock in Hertz. param tcrPrescaleValue The TCR prescale value needed to program the TCR. return The actual calculated baud rate. This function may also return a "0" if the LPSPI is not configured for master mode or if the LPSPI module is not disabled.

Definition at line 420 of file fsl_lpspi.c.

{
    assert(tcrPrescaleValue);
 
    /* For master mode configuration only, if slave mode detected, return 0.
    * Also, the LPSPI module needs to be disabled first, if enabled, return 0
    */
    if ((!LPSPI_IsMaster(base)) || (base->CR & LPSPI_CR_MEN_MASK))
    {
        return 0;
    }
 
    uint32_t prescaler, bestPrescaler;
    uint32_t scaler, bestScaler;
    uint32_t realBaudrate, bestBaudrate;
    uint32_t diff, min_diff;
    uint32_t desiredBaudrate = baudRate_Bps;
 
    /* find combination of prescaler and scaler resulting in baudrate closest to the
    * requested value
    */
    min_diff = 0xFFFFFFFFU;
 
    /* Set to maximum divisor value bit settings so that if baud rate passed in is less
    * than the minimum possible baud rate, then the SPI will be configured to the lowest
    * possible baud rate
    */
    bestPrescaler = 7;
    bestScaler = 255;
 
    bestBaudrate = 0; /* required to avoid compilation warning */
 
    /* In all for loops, if min_diff = 0, the exit for loop*/
    for (prescaler = 0; (prescaler < 8) && min_diff; prescaler++)
    {
        for (scaler = 0; (scaler < 256) && min_diff; scaler++)
        {
            realBaudrate = (srcClock_Hz / (s_baudratePrescaler[prescaler] * (scaler + 2U)));
 
            /* calculate the baud rate difference based on the conditional statement
            * that states that the calculated baud rate must not exceed the desired baud rate
            */
            if (desiredBaudrate >= realBaudrate)
            {
                diff = desiredBaudrate - realBaudrate;
                if (min_diff > diff)
                {
                    /* a better match found */
                    min_diff = diff;
                    bestPrescaler = prescaler;
                    bestScaler = scaler;
                    bestBaudrate = realBaudrate;
                }
            }
        }
    }
 
    /* Write the best baud rate scalar to the CCR.
    * Note, no need to check for error since we've already checked to make sure the module is
    * disabled and in master mode. Also, there is a limit on the maximum divider so we will not
    * exceed this.
    */
    base->CCR = (base->CCR & ~LPSPI_CCR_SCKDIV_MASK) | LPSPI_CCR_SCKDIV(bestScaler);
 
    /* return the best prescaler value for user to use later */
    *tcrPrescaleValue = bestPrescaler;
 
    /* return the actual calculated baud rate */
    return bestBaudrate;
}

Referenced by LPSPI_MasterInit().

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LPSPI_MasterSetDelayScaler()

void LPSPI_MasterSetDelayScaler	(	LPSPI_Type *	base,
		uint32_t	scaler,
		lpspi_delay_type_t	whichDelay
	)

Manually configures a specific LPSPI delay parameter (module must be disabled to change the delay values).

This function configures the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.

The delay names are available in type lpspi_delay_type_t.

The user passes the desired delay along with the delay value. This allows the user to directly set the delay values if they have pre-calculated them or if they simply wish to manually increment the value.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters

base	LPSPI peripheral address.
scaler	The 8-bit delay value 0x00 to 0xFF (255).
whichDelay	The desired delay to configure, must be of type lpspi_delay_type_t.

brief Manually configures a specific LPSPI delay parameter (module must be disabled to change the delay values).

This function configures the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.

The delay names are available in type lpspi_delay_type_t.

The user passes the desired delay along with the delay value. This allows the user to directly set the delay values if they have pre-calculated them or if they simply wish to manually increment the value.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

param base LPSPI peripheral address. param scaler The 8-bit delay value 0x00 to 0xFF (255). param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t.

Definition at line 516 of file fsl_lpspi.c.

{
    /*These settings are only relevant in master mode */
    switch (whichDelay)
    {
        case kLPSPI_PcsToSck:
            base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler);
 
            break;
        case kLPSPI_LastSckToPcs:
            base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler);
 
            break;
        case kLPSPI_BetweenTransfer:
            base->CCR = (base->CCR & (~LPSPI_CCR_DBT_MASK)) | LPSPI_CCR_DBT(scaler);
 
            break;
        default:
            assert(false);
            break;
    }
}

Referenced by LPSPI_MasterSetDelayTimes().

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LPSPI_MasterSetDelayTimes()

uint32_t LPSPI_MasterSetDelayTimes	(	LPSPI_Type *	base,
		uint32_t	delayTimeInNanoSec,
		lpspi_delay_type_t	whichDelay,
		uint32_t	srcClock_Hz
	)

Calculates the delay based on the desired delay input in nanoseconds (module must be disabled to change the delay values).

This function calculates the values for the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.

The delay names are available in type lpspi_delay_type_t.

The user passes the desired delay and the desired delay value in nano-seconds. The function calculates the value needed for the desired delay parameter and returns the actual calculated delay because an exact delay match may not be possible. In this case, the closest match is calculated without going below the desired delay value input. It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum supported delay is returned. It is up to the higher level peripheral driver to alert the user of an out of range delay input.

Note that the LPSPI module must be configured for master mode before configuring this. And note that the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler).

Parameters

base	LPSPI peripheral address.
delayTimeInNanoSec	The desired delay value in nano-seconds.
whichDelay	The desired delay to configuration, which must be of type lpspi_delay_type_t.
srcClock_Hz	Module source input clock in Hertz.

Returns

actual Calculated delay value in nano-seconds.

brief Calculates the delay based on the desired delay input in nanoseconds (module must be disabled to change the delay values).

This function calculates the values for the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.

The delay names are available in type lpspi_delay_type_t.

The user passes the desired delay and the desired delay value in nano-seconds. The function calculates the value needed for the desired delay parameter and returns the actual calculated delay because an exact delay match may not be possible. In this case, the closest match is calculated without going below the desired delay value input. It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum supported delay is returned. It is up to the higher level peripheral driver to alert the user of an out of range delay input.

Note that the LPSPI module must be configured for master mode before configuring this. And note that the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler).

param base LPSPI peripheral address. param delayTimeInNanoSec The desired delay value in nano-seconds. param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. param srcClock_Hz Module source input clock in Hertz. return actual Calculated delay value in nano-seconds.

Definition at line 567 of file fsl_lpspi.c.

{
    uint64_t realDelay, bestDelay;
    uint32_t scaler, bestScaler;
    uint32_t diff, min_diff;
    uint64_t initialDelayNanoSec;
    uint32_t clockDividedPrescaler;
 
    /* For delay between transfer, an additional scaler value is needed */
    uint32_t additionalScaler = 0;
 
    /*As the RM note, the LPSPI baud rate clock is itself divided by the PRESCALE setting, which can vary between
     * transfers.*/
    clockDividedPrescaler =
        srcClock_Hz / s_baudratePrescaler[(base->TCR & LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIFT];
 
    /* Find combination of prescaler and scaler resulting in the delay closest to the requested value.*/
    min_diff = 0xFFFFFFFFU;
 
    /* Initialize scaler to max value to generate the max delay */
    bestScaler = 0xFFU;
 
    /* Calculate the initial (min) delay and maximum possible delay based on the specific delay as
    * the delay divisors are slightly different based on which delay we are configuring.
    */
    if (whichDelay == kLPSPI_BetweenTransfer)
    {
        /* First calculate the initial, default delay, note min delay is 2 clock cycles. Due to large size of
         calculated values (uint64_t), we need to break up the calculation into several steps to ensure
         accurate calculated results
         */
        initialDelayNanoSec = 1000000000U;
        initialDelayNanoSec *= 2U;
        initialDelayNanoSec /= clockDividedPrescaler;
 
        /* Calculate the maximum delay */
        bestDelay = 1000000000U;
        bestDelay *= 257U; /* based on DBT+2, or 255 + 2 */
        bestDelay /= clockDividedPrescaler;
 
        additionalScaler = 1U;
    }
    else
    {
        /* First calculate the initial, default delay, min delay is 1 clock cycle. Due to large size of calculated
        values (uint64_t), we need to break up the calculation into several steps to ensure accurate calculated
        results.
        */
        initialDelayNanoSec = 1000000000U;
        initialDelayNanoSec /= clockDividedPrescaler;
 
        /* Calculate the maximum delay */
        bestDelay = 1000000000U;
        bestDelay *= 256U; /* based on SCKPCS+1 or PCSSCK+1, or 255 + 1 */
        bestDelay /= clockDividedPrescaler;
 
        additionalScaler = 0;
    }
 
    /* If the initial, default delay is already greater than the desired delay, then
    * set the delay to their initial value (0) and return the delay. In other words,
    * there is no way to decrease the delay value further.
    */
    if (initialDelayNanoSec >= delayTimeInNanoSec)
    {
        LPSPI_MasterSetDelayScaler(base, 0, whichDelay);
        return initialDelayNanoSec;
    }
 
    /* If min_diff = 0, the exit for loop */
    for (scaler = 0; (scaler < 256U) && min_diff; scaler++)
    {
        /* Calculate the real delay value as we cycle through the scaler values.
        Due to large size of calculated values (uint64_t), we need to break up the
        calculation into several steps to ensure accurate calculated results
        */
        realDelay = 1000000000U;
        realDelay *= (scaler + 1 + additionalScaler);
        realDelay /= clockDividedPrescaler;
 
        /* calculate the delay difference based on the conditional statement
        * that states that the calculated delay must not be less then the desired delay
        */
        if (realDelay >= delayTimeInNanoSec)
        {
            diff = realDelay - delayTimeInNanoSec;
            if (min_diff > diff)
            {
                /* a better match found */
                min_diff = diff;
                bestScaler = scaler;
                bestDelay = realDelay;
            }
        }
    }
 
    /* write the best scaler value for the delay */
    LPSPI_MasterSetDelayScaler(base, bestScaler, whichDelay);
 
    /* return the actual calculated delay value (in ns) */
    return bestDelay;
}

Referenced by LPSPI_MasterInit().

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LPSPI_MasterTransferAbort()

void LPSPI_MasterTransferAbort	(	LPSPI_Type *	base,
		lpspi_master_handle_t *	handle
	)

LPSPI master abort transfer which uses an interrupt method.

This function aborts a transfer which uses an interrupt method.

Parameters

base	LPSPI peripheral address.
handle	pointer to lpspi_master_handle_t structure which stores the transfer state.

brief LPSPI master abort transfer which uses an interrupt method.

This function aborts a transfer which uses an interrupt method.

param base LPSPI peripheral address. param handle pointer to lpspi_master_handle_t structure which stores the transfer state.

Definition at line 1235 of file fsl_lpspi.c.

{
    assert(handle);
 
    /* Disable interrupt requests*/
    LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable);
 
    LPSPI_Reset(base);
 
    handle->state = kLPSPI_Idle;
    handle->txRemainingByteCount = 0;
    handle->rxRemainingByteCount = 0;
}

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LPSPI_MasterTransferBlocking()

status_t LPSPI_MasterTransferBlocking	(	LPSPI_Type *	base,
		lpspi_transfer_t *	transfer
	)

LPSPI master transfer data using a polling method.

This function transfers data using a polling method. This is a blocking function, which does not return until all transfers have been completed.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters

base	LPSPI peripheral address.
transfer	pointer to lpspi_transfer_t structure.

Returns

status of status_t.

brief LPSPI master transfer data using a polling method.

This function transfers data using a polling method. This is a blocking function, which does not return until all transfers have been completed.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

param base LPSPI peripheral address. param transfer pointer to lpspi_transfer_t structure. return status of status_t.

Definition at line 779 of file fsl_lpspi.c.

{
    assert(transfer);
 
    uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
    uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8;
    uint32_t temp = 0U;
    uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)];
 
    if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame))
    {
        return kStatus_InvalidArgument;
    }
 
    /* Check that LPSPI is not busy.*/
    if (LPSPI_GetStatusFlags(base) & kLPSPI_ModuleBusyFlag)
    {
        return kStatus_LPSPI_Busy;
    }
 
    uint8_t *txData = transfer->txData;
    uint8_t *rxData = transfer->rxData;
    uint32_t txRemainingByteCount = transfer->dataSize;
    uint32_t rxRemainingByteCount = transfer->dataSize;
 
    uint8_t bytesEachWrite;
    uint8_t bytesEachRead;
 
    uint32_t readData = 0;
    uint32_t wordToSend =
        ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24);
 
    /*The TX and RX FIFO sizes are always the same*/
    uint32_t fifoSize = LPSPI_GetRxFifoSize(base);
 
    uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT;
 
    bool isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous);
    bool isRxMask = false;
    bool isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap);
 
    LPSPI_FlushFifo(base, true, true);
    LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag);
 
    if (!rxData)
    {
        isRxMask = true;
    }
 
    LPSPI_Enable(base, false);
    base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK);
    /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */
    temp = base->CFGR1;
    temp &= LPSPI_CFGR1_PINCFG_MASK;
    if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut)))
    {
        if (!txData)
        {
            base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK;
        }
        /* The 3-wire mode can't send and receive data at the same time. */
        if ((txData) && (rxData))
        {
            return kStatus_InvalidArgument;
        }
    }
    LPSPI_Enable(base, true);
 
    base->TCR =
        (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) |
        LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_PCS(whichPcs);
 
    if (bytesPerFrame <= 4)
    {
        bytesEachWrite = bytesPerFrame;
        bytesEachRead = bytesPerFrame;
    }
    else
    {
        bytesEachWrite = 4;
        bytesEachRead = 4;
    }
    
    /*Write the TX data until txRemainingByteCount is equal to 0 */
    while (txRemainingByteCount > 0)
    {
        if (txRemainingByteCount < bytesEachWrite)
        {
            bytesEachWrite = txRemainingByteCount;
        }
 
        /*Wait until TX FIFO is not full*/
        while (LPSPI_GetTxFifoCount(base) == fifoSize)
        {
        }
 
        if (txData)
        {
            wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap);
            txData += bytesEachWrite;
        }
 
        LPSPI_WriteData(base, wordToSend);
        txRemainingByteCount -= bytesEachWrite;
 
        /*Check whether there is RX data in RX FIFO . Read out the RX data so that the RX FIFO would not overrun.*/
        if (rxData)
        {
            while (LPSPI_GetRxFifoCount(base))
            {
                readData = LPSPI_ReadData(base);
                if (rxRemainingByteCount < bytesEachRead)
                {
                    bytesEachRead = rxRemainingByteCount;
                }
 
                LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap);
                rxData += bytesEachRead;
 
                rxRemainingByteCount -= bytesEachRead;
            }
        }
    }
 
    /* After write all the data in TX FIFO , should write the TCR_CONTC to 0 to de-assert the PCS. Note that TCR
     * register also use the TX FIFO.
     */
    while ((LPSPI_GetTxFifoCount(base) == fifoSize))
    {
    }
    base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK));
 
    /*Read out the RX data in FIFO*/
    if (rxData)
    {
        while (rxRemainingByteCount > 0)
        {
            while (LPSPI_GetRxFifoCount(base))
            {
                readData = LPSPI_ReadData(base);
 
                if (rxRemainingByteCount < bytesEachRead)
                {
                    bytesEachRead = rxRemainingByteCount;
                }
 
                LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap);
                rxData += bytesEachRead;
 
                rxRemainingByteCount -= bytesEachRead;
            }
        }
    }
    else
    {
        /* If no RX buffer, then transfer is not complete until transfer complete flag sets */
        while (!(LPSPI_GetStatusFlags(base) & kLPSPI_TransferCompleteFlag))
        {
        }
    }
 
    return kStatus_Success;
}

Referenced by spi_lld_polled_exchange().

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LPSPI_MasterTransferCreateHandle()

void LPSPI_MasterTransferCreateHandle	(	LPSPI_Type *	base,
		lpspi_master_handle_t *	handle,
		lpspi_master_transfer_callback_t	callback,
		void *	userData
	)

Initializes the LPSPI master handle.

This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters

base	LPSPI peripheral address.
handle	LPSPI handle pointer to lpspi_master_handle_t.
callback	DSPI callback.
userData	callback function parameter.

brief Initializes the LPSPI master handle.

This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

param base LPSPI peripheral address. param handle LPSPI handle pointer to lpspi_master_handle_t. param callback DSPI callback. param userData callback function parameter.

Definition at line 686 of file fsl_lpspi.c.

{
    assert(handle);
 
    /* Zero the handle. */
    memset(handle, 0, sizeof(*handle));
 
    s_lpspiHandle[LPSPI_GetInstance(base)] = handle;
 
    /* Set irq handler. */
    s_lpspiMasterIsr = LPSPI_MasterTransferHandleIRQ;
 
    handle->callback = callback;
    handle->userData = userData;
}

Referenced by spi_lld_start().

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LPSPI_MasterTransferGetCount()

status_t LPSPI_MasterTransferGetCount	(	LPSPI_Type *	base,
		lpspi_master_handle_t *	handle,
		size_t *	count
	)

Gets the master transfer remaining bytes.

This function gets the master transfer remaining bytes.

Parameters

base	LPSPI peripheral address.
handle	pointer to lpspi_master_handle_t structure which stores the transfer state.
count	Number of bytes transferred so far by the non-blocking transaction.

Returns

status of status_t.

brief Gets the master transfer remaining bytes.

This function gets the master transfer remaining bytes.

param base LPSPI peripheral address. param handle pointer to lpspi_master_handle_t structure which stores the transfer state. param count Number of bytes transferred so far by the non-blocking transaction. return status of status_t.

Definition at line 1195 of file fsl_lpspi.c.

{
    assert(handle);
 
    if (!count)
    {
        return kStatus_InvalidArgument;
    }
 
    /* Catch when there is not an active transfer. */
    if (handle->state != kLPSPI_Busy)
    {
        *count = 0;
        return kStatus_NoTransferInProgress;
    }
 
    size_t remainingByte;
 
    if (handle->rxData)
    {
        remainingByte = handle->rxRemainingByteCount;
    }
    else
    {
        remainingByte = handle->txRemainingByteCount;
    }
 
    *count = handle->totalByteCount - remainingByte;
 
    return kStatus_Success;
}

LPSPI_MasterTransferHandleIRQ()

void LPSPI_MasterTransferHandleIRQ	(	LPSPI_Type *	base,
		lpspi_master_handle_t *	handle
	)

LPSPI Master IRQ handler function.

This function processes the LPSPI transmit and receive IRQ.

Parameters

base	LPSPI peripheral address.
handle	pointer to lpspi_master_handle_t structure which stores the transfer state.

brief LPSPI Master IRQ handler function.

This function processes the LPSPI transmit and receive IRQ.

param base LPSPI peripheral address. param handle pointer to lpspi_master_handle_t structure which stores the transfer state.

Definition at line 1257 of file fsl_lpspi.c.

{
    assert(handle);
 
    uint32_t readData;
 
    if (handle->rxData != NULL)
    {
        if (handle->rxRemainingByteCount)
        {
            /* First, disable the interrupts to avoid potentially triggering another interrupt
            * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll
            * re-enable the interrupts based on the LPSPI state after reading out the FIFO.
            */
            LPSPI_DisableInterrupts(base, kLPSPI_RxInterruptEnable);
 
            while ((LPSPI_GetRxFifoCount(base)) && (handle->rxRemainingByteCount))
            {
                /*Read out the data*/
                readData = LPSPI_ReadData(base);
 
                /*Decrease the read RX register times.*/
                --handle->readRegRemainingTimes;
 
                if (handle->rxRemainingByteCount < handle->bytesEachRead)
                {
                    handle->bytesEachRead = handle->rxRemainingByteCount;
                }
 
                LPSPI_SeparateReadData(handle->rxData, readData, handle->bytesEachRead, handle->isByteSwap);
                handle->rxData += handle->bytesEachRead;
 
                /*Decrease the remaining RX byte count.*/
                handle->rxRemainingByteCount -= handle->bytesEachRead;
            }
 
            /* Re-enable the interrupts only if rxCount indicates there is more data to receive,
            * else we may get a spurious interrupt.
            * */
            if (handle->rxRemainingByteCount)
            {
                /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */
                LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable);
            }
        }
 
        /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there
         *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark.
         */
        if ((handle->readRegRemainingTimes) <= (handle->rxWatermark))
        {
            base->FCR =
                (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) |
                LPSPI_FCR_RXWATER((handle->readRegRemainingTimes > 1) ? (handle->readRegRemainingTimes - 1U) : (0U));
        }
    }
 
    if (handle->txRemainingByteCount)
    {
        LPSPI_MasterTransferFillUpTxFifo(base, handle);
    }
    else
    {
        if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize)))
        {
            if ((handle->isPcsContinuous) && (handle->writeTcrInIsr))
            {
                base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK));
                handle->writeTcrInIsr = false;
            }
        }
    }
 
    if ((handle->txRemainingByteCount == 0) && (handle->rxRemainingByteCount == 0) && (!handle->writeTcrInIsr))
    {
        /* If no RX buffer, then transfer is not complete until transfer complete flag sets */
        if (handle->rxData == NULL)
        {
            if (LPSPI_GetStatusFlags(base) & kLPSPI_TransferCompleteFlag)
            {
                /* Complete the transfer and disable the interrupts */
                LPSPI_MasterTransferComplete(base, handle);
            }
            else
            {
                LPSPI_EnableInterrupts(base, kLPSPI_TransferCompleteInterruptEnable);
                LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable);
            }
        }
        else
        {
            /* Complete the transfer and disable the interrupts */
            LPSPI_MasterTransferComplete(base, handle);
        }
    }
}

Referenced by LPSPI_MasterTransferCreateHandle().

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LPSPI_MasterTransferNonBlocking()

status_t LPSPI_MasterTransferNonBlocking	(	LPSPI_Type *	base,
		lpspi_master_handle_t *	handle,
		lpspi_transfer_t *	transfer
	)

LPSPI master transfer data using an interrupt method.

This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters

base	LPSPI peripheral address.
handle	pointer to lpspi_master_handle_t structure which stores the transfer state.
transfer	pointer to lpspi_transfer_t structure.

Returns

status of status_t.

brief LPSPI master transfer data using an interrupt method.

This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

param base LPSPI peripheral address. param handle pointer to lpspi_master_handle_t structure which stores the transfer state. param transfer pointer to lpspi_transfer_t structure. return status of status_t.

Definition at line 961 of file fsl_lpspi.c.

{
    assert(handle);
    assert(transfer);
 
    uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
    uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8;
    uint32_t temp = 0U;
    uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)];
 
    if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame))
    {
        return kStatus_InvalidArgument;
    }
 
    /* Check that we're not busy.*/
    if (handle->state == kLPSPI_Busy)
    {
        return kStatus_LPSPI_Busy;
    }
 
    handle->state = kLPSPI_Busy;
 
    bool isRxMask = false;
 
    uint8_t txWatermark;
 
    uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT;
 
    handle->txData = transfer->txData;
    handle->rxData = transfer->rxData;
    handle->txRemainingByteCount = transfer->dataSize;
    handle->rxRemainingByteCount = transfer->dataSize;
    handle->totalByteCount = transfer->dataSize;
 
    handle->writeTcrInIsr = false;
 
    handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4);
    handle->readRegRemainingTimes = handle->writeRegRemainingTimes;
 
    handle->txBuffIfNull =
        ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24);
 
    /*The TX and RX FIFO sizes are always the same*/
    handle->fifoSize = LPSPI_GetRxFifoSize(base);
 
    handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous);
    handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap);
 
    /*Set the RX and TX watermarks to reduce the ISR times.*/
    if (handle->fifoSize > 1)
    {
        txWatermark = 1;
        handle->rxWatermark = handle->fifoSize - 2;
    }
    else
    {
        txWatermark = 0;
        handle->rxWatermark = 0;
    }
 
    LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark);
 
    LPSPI_Enable(base, false);
    /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */
    base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK);
    /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */
    temp = base->CFGR1;
    temp &= LPSPI_CFGR1_PINCFG_MASK;
    if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut)))
    {
        if (!handle->txData)
        {
            base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK;
        }
        /* The 3-wire mode can't send and receive data at the same time. */
        if ((handle->txData) && (handle->rxData))
        {
            return kStatus_InvalidArgument;
        }
    }
    LPSPI_Enable(base, true);
 
    /*Flush FIFO , clear status , disable all the inerrupts.*/
    LPSPI_FlushFifo(base, true, true);
    LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag);
    LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable);
 
    /* If there is not rxData , can mask the receive data (receive data is not stored in receive FIFO).
     * For master transfer , we'd better not masked the transmit data in TCR since the transfer flow is hard to
     * controlled by software.*/
    if (handle->rxData == NULL)
    {
        isRxMask = true;
        handle->rxRemainingByteCount = 0;
    }
 
    base->TCR =
        (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) |
        LPSPI_TCR_CONT(handle->isPcsContinuous) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) |
        LPSPI_TCR_PCS(whichPcs);
 
    /*Calculate the bytes for write/read the TX/RX register each time*/
    if (bytesPerFrame <= 4)
    {
        handle->bytesEachWrite = bytesPerFrame;
        handle->bytesEachRead = bytesPerFrame;
    }
    else
    {
        handle->bytesEachWrite = 4;
        handle->bytesEachRead = 4;
    }
 
    /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX ,
     * and you should also enable the INTMUX interupt in your application.
     */
    EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]);
 
    /*TCR is also shared the FIFO , so wait for TCR written.*/
    while (LPSPI_GetTxFifoCount(base) != 0)
    {
    }
    /*Fill up the TX data in FIFO */
    LPSPI_MasterTransferFillUpTxFifo(base, handle);
 
    /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data.
     * The IRQ handler will get the status of RX and TX interrupt flags.
     */
    if (handle->rxData)
    {
        /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there
         *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark.
         */
        if ((handle->readRegRemainingTimes) <= handle->rxWatermark)
        {
            base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->readRegRemainingTimes - 1);
        }
 
        LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable);
    }
    else
    {
        LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable);
    }
 
    return kStatus_Success;
}

Referenced by spi_lld_exchange(), spi_lld_receive(), and spi_lld_send().

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LPSPI_ReadData()

static uint32_t LPSPI_ReadData ( LPSPI_Type *  base )

inlinestatic

Reads data from the data buffer.

This function reads the data from the Receive Data Register (RDR). This function can be used for either master or slave mode.

Parameters

base	LPSPI peripheral address.

Returns

The data read from the data buffer.

Definition at line 918 of file fsl_lpspi.h.

{
    return (base->RDR);
}

Referenced by EDMA_LpspiMasterCallback(), EDMA_LpspiSlaveCallback(), LPSPI_MasterTransferBlocking(), LPSPI_MasterTransferHandleIRQ(), and LPSPI_SlaveTransferHandleIRQ().

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LPSPI_Reset()

void LPSPI_Reset

(

LPSPI_Type *

base

)

Restores the LPSPI peripheral to reset state. Note that this function sets all registers to reset state. As a result, the LPSPI module can't work after calling this API.

Parameters

base	LPSPI peripheral address.

brief Restores the LPSPI peripheral to reset state. Note that this function sets all registers to reset state. As a result, the LPSPI module can't work after calling this API. param base LPSPI peripheral address.

Definition at line 351 of file fsl_lpspi.c.

{
    /* Reset all internal logic and registers, except the Control Register. Remains set until cleared by software.*/
    base->CR |= LPSPI_CR_RST_MASK;
 
    /* Software reset doesn't reset the CR, so manual reset the FIFOs */
    base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK;
 
    /* Master logic is not reset and module is disabled.*/
    base->CR = 0x00U;
}

Referenced by LPSPI_Deinit(), LPSPI_MasterTransferAbort(), and LPSPI_SlaveTransferAbort().

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LPSPI_SetAllPcsPolarity()

static void LPSPI_SetAllPcsPolarity ( LPSPI_Type *  base, uint32_t  mask  )

inlinestatic

Configures all LPSPI peripheral chip select polarities simultaneously.

Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).

This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of PCS is device-specific.

LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow);

Parameters

base	LPSPI peripheral address.
mask	The PCS polarity mask; Use the enum _lpspi_pcs_polarity.

Definition at line 778 of file fsl_lpspi.h.

{
    base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask);
}

LPSPI_SetDummyData()

void LPSPI_SetDummyData	(	LPSPI_Type *	base,
		uint8_t	dummyData
	)

Set up the dummy data.

Parameters

base	LPSPI peripheral address.
dummyData	Data to be transferred when tx buffer is NULL. Note: This API has no effect when LPSPI in slave interrupt mode, because driver will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit FIFO and output pin is tristated.

brief Set up the dummy data.

param base LPSPI peripheral address. param dummyData Data to be transferred when tx buffer is NULL. Note: This API has no effect when LPSPI in slave interrupt mode, because driver will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit FIFO and output pin is tristated.

Definition at line 174 of file fsl_lpspi.c.

{
    uint32_t instance = LPSPI_GetInstance(base);
    g_lpspiDummyData[instance] = dummyData;
}

Referenced by LPSPI_MasterInit(), and LPSPI_SlaveInit().

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LPSPI_SetFifoWatermarks()

static void LPSPI_SetFifoWatermarks ( LPSPI_Type *  base, uint32_t  txWater, uint32_t  rxWater  )

inlinestatic

Sets the transmit and receive FIFO watermark values.

This function allows the user to set the receive and transmit FIFO watermarks. The function does not compare the watermark settings to the FIFO size. The FIFO watermark should not be equal to or greater than the FIFO size. It is up to the higher level driver to make this check.

Parameters

base	LPSPI peripheral address.
txWater	The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.
rxWater	The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.

Definition at line 759 of file fsl_lpspi.h.

{
    base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater);
}

Referenced by LPSPI_MasterInit(), LPSPI_MasterTransferEDMA(), LPSPI_MasterTransferNonBlocking(), LPSPI_SlaveInit(), LPSPI_SlaveTransferEDMA(), and LPSPI_SlaveTransferNonBlocking().

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LPSPI_SetFrameSize()

static void LPSPI_SetFrameSize ( LPSPI_Type *  base, uint32_t  frameSize  )

inlinestatic

Configures the frame size.

The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.

Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command register should only be changed if the LPSPI is idle.

Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That means the TCR register should be written to when the Tx FIFO is not full.

Parameters

base	LPSPI peripheral address.
frameSize	The frame size in number of bits.

Definition at line 802 of file fsl_lpspi.h.

{
    base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1);
}

LPSPI_SetMasterSlaveMode()

static void LPSPI_SetMasterSlaveMode ( LPSPI_Type *  base, lpspi_master_slave_mode_t  mode  )

inlinestatic

Configures the LPSPI for either master or slave.

Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).

Parameters

base	LPSPI peripheral address.
mode	Mode setting (master or slave) of type lpspi_master_slave_mode_t.

Definition at line 720 of file fsl_lpspi.h.

{
    base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode);
}

Referenced by LPSPI_MasterInit(), and LPSPI_SlaveInit().

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LPSPI_SlaveGetDefaultConfig()

void LPSPI_SlaveGetDefaultConfig

(

lpspi_slave_config_t *

slaveConfig

)

Sets the lpspi_slave_config_t structure to default values.

This API initializes the configuration structure for LPSPI_SlaveInit(). The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified before calling the LPSPI_SlaveInit(). Example:

lpspi_slave_config_t  slaveConfig;
LPSPI_SlaveGetDefaultConfig(&slaveConfig);

Parameters

slaveConfig

pointer to lpspi_slave_config_t structure.

brief Sets the lpspi_slave_config_t structure to default values.

This API initializes the configuration structure for LPSPI_SlaveInit(). The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified before calling the LPSPI_SlaveInit(). Example: code lpspi_slave_config_t slaveConfig; LPSPI_SlaveGetDefaultConfig(&slaveConfig); endcode param slaveConfig pointer to lpspi_slave_config_t structure.

< Bits per frame, minimum 8, maximum 4096.

< Clock polarity.

< Clock phase.

< MSB or LSB data shift direction.

< Desired Peripheral Chip Select (pcs)

< Desired PCS active high or low

Definition at line 326 of file fsl_lpspi.c.

{
    assert(slaveConfig);
 
    /* Initializes the configure structure to zero. */
    memset(slaveConfig, 0, sizeof(*slaveConfig));
 
    slaveConfig->bitsPerFrame = 8;                      /*!< Bits per frame, minimum 8, maximum 4096.*/
    slaveConfig->cpol = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */
    slaveConfig->cpha = kLPSPI_ClockPhaseFirstEdge;     /*!< Clock phase. */
    slaveConfig->direction = kLPSPI_MsbFirst;           /*!< MSB or LSB data shift direction. */
 
    slaveConfig->whichPcs = kLPSPI_Pcs0;                   /*!< Desired Peripheral Chip Select (pcs) */
    slaveConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; /*!< Desired PCS active high or low */
 
    slaveConfig->pinCfg = kLPSPI_SdiInSdoOut;
    slaveConfig->dataOutConfig = kLpspiDataOutRetained;
}

Referenced by spi_lld_start().

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LPSPI_SlaveInit()

void LPSPI_SlaveInit	(	LPSPI_Type *	base,
		const lpspi_slave_config_t *	slaveConfig
	)

LPSPI slave configuration.

Parameters

base	LPSPI peripheral address.
slaveConfig	Pointer to a structure lpspi_slave_config_t.

brief LPSPI slave configuration.

param base LPSPI peripheral address. param slaveConfig Pointer to a structure lpspi_slave_config_t.

Definition at line 279 of file fsl_lpspi.c.

{
    assert(slaveConfig);
 
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 
    uint32_t instance = LPSPI_GetInstance(base);
    /* Enable LPSPI clock */
    CLOCK_EnableClock(s_lpspiClocks[instance]);
 
#if defined(LPSPI_PERIPH_CLOCKS)
    CLOCK_EnableClock(s_LpspiPeriphClocks[instance]);
#endif
 
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
    LPSPI_SetMasterSlaveMode(base, kLPSPI_Slave);
 
    LPSPI_SetOnePcsPolarity(base, slaveConfig->whichPcs, slaveConfig->pcsActiveHighOrLow);
 
    base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) |
                  LPSPI_CFGR1_OUTCFG(slaveConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(slaveConfig->pinCfg);
 
    LPSPI_SetFifoWatermarks(base, kLpspiDefaultTxWatermark, kLpspiDefaultRxWatermark);
 
    base->TCR = LPSPI_TCR_CPOL(slaveConfig->cpol) | LPSPI_TCR_CPHA(slaveConfig->cpha) |
                LPSPI_TCR_LSBF(slaveConfig->direction) | LPSPI_TCR_FRAMESZ(slaveConfig->bitsPerFrame - 1);
 
    /* This operation will set the dummy data for edma transfer, no effect in interrupt way. */
    LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA);
 
    LPSPI_Enable(base, true);
}

Referenced by spi_lld_start().

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LPSPI_SlaveTransferAbort()

void LPSPI_SlaveTransferAbort	(	LPSPI_Type *	base,
		lpspi_slave_handle_t *	handle
	)

LPSPI slave aborts a transfer which uses an interrupt method.

This function aborts a transfer which uses an interrupt method.

Parameters

base	LPSPI peripheral address.
handle	pointer to lpspi_slave_handle_t structure which stores the transfer state.

brief LPSPI slave aborts a transfer which uses an interrupt method.

This function aborts a transfer which uses an interrupt method.

param base LPSPI peripheral address. param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.

Definition at line 1669 of file fsl_lpspi.c.

{
    assert(handle);
 
    /* Disable interrupt requests*/
    LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable);
 
    LPSPI_Reset(base);
 
    handle->state = kLPSPI_Idle;
    handle->txRemainingByteCount = 0;
    handle->rxRemainingByteCount = 0;
}

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LPSPI_SlaveTransferCreateHandle()

void LPSPI_SlaveTransferCreateHandle	(	LPSPI_Type *	base,
		lpspi_slave_handle_t *	handle,
		lpspi_slave_transfer_callback_t	callback,
		void *	userData
	)

Initializes the LPSPI slave handle.

This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters

base	LPSPI peripheral address.
handle	LPSPI handle pointer to lpspi_slave_handle_t.
callback	DSPI callback.
userData	callback function parameter.

brief Initializes the LPSPI slave handle.

This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

param base LPSPI peripheral address. param handle LPSPI handle pointer to lpspi_slave_handle_t. param callback DSPI callback. param userData callback function parameter.

Definition at line 1366 of file fsl_lpspi.c.

{
    assert(handle);
 
    /* Zero the handle. */
    memset(handle, 0, sizeof(*handle));
 
    s_lpspiHandle[LPSPI_GetInstance(base)] = handle;
 
    /* Set irq handler. */
    s_lpspiSlaveIsr = LPSPI_SlaveTransferHandleIRQ;
 
    handle->callback = callback;
    handle->userData = userData;
}

Referenced by spi_lld_start().

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LPSPI_SlaveTransferGetCount()

status_t LPSPI_SlaveTransferGetCount	(	LPSPI_Type *	base,
		lpspi_slave_handle_t *	handle,
		size_t *	count
	)

Gets the slave transfer remaining bytes.

This function gets the slave transfer remaining bytes.

Parameters

base	LPSPI peripheral address.
handle	pointer to lpspi_slave_handle_t structure which stores the transfer state.
count	Number of bytes transferred so far by the non-blocking transaction.

Returns

status of status_t.

brief Gets the slave transfer remaining bytes.

This function gets the slave transfer remaining bytes.

param base LPSPI peripheral address. param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. param count Number of bytes transferred so far by the non-blocking transaction. return status of status_t.

Definition at line 1629 of file fsl_lpspi.c.

{
    assert(handle);
 
    if (!count)
    {
        return kStatus_InvalidArgument;
    }
 
    /* Catch when there is not an active transfer. */
    if (handle->state != kLPSPI_Busy)
    {
        *count = 0;
        return kStatus_NoTransferInProgress;
    }
 
    size_t remainingByte;
 
    if (handle->rxData)
    {
        remainingByte = handle->rxRemainingByteCount;
    }
    else
    {
        remainingByte = handle->txRemainingByteCount;
    }
 
    *count = handle->totalByteCount - remainingByte;
 
    return kStatus_Success;
}

LPSPI_SlaveTransferHandleIRQ()

void LPSPI_SlaveTransferHandleIRQ	(	LPSPI_Type *	base,
		lpspi_slave_handle_t *	handle
	)

LPSPI Slave IRQ handler function.

This function processes the LPSPI transmit and receives an IRQ.

Parameters

base	LPSPI peripheral address.
handle	pointer to lpspi_slave_handle_t structure which stores the transfer state.

brief LPSPI Slave IRQ handler function.

This function processes the LPSPI transmit and receives an IRQ.

param base LPSPI peripheral address. param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.

Definition at line 1691 of file fsl_lpspi.c.

{
    assert(handle);
 
    uint32_t readData;   /* variable to store word read from RX FIFO */
    uint32_t wordToSend; /* variable to store word to write to TX FIFO */
 
    if (handle->rxData != NULL)
    {
        if (handle->rxRemainingByteCount > 0)
        {
            while (LPSPI_GetRxFifoCount(base))
            {
                /*Read out the data*/
                readData = LPSPI_ReadData(base);
 
                /*Decrease the read RX register times.*/
                --handle->readRegRemainingTimes;
 
                if (handle->rxRemainingByteCount < handle->bytesEachRead)
                {
                    handle->bytesEachRead = handle->rxRemainingByteCount;
                }
 
                LPSPI_SeparateReadData(handle->rxData, readData, handle->bytesEachRead, handle->isByteSwap);
                handle->rxData += handle->bytesEachRead;
 
                /*Decrease the remaining RX byte count.*/
                handle->rxRemainingByteCount -= handle->bytesEachRead;
 
                if ((handle->txRemainingByteCount > 0) && (handle->txData != NULL))
                {
                    if (handle->txRemainingByteCount < handle->bytesEachWrite)
                    {
                        handle->bytesEachWrite = handle->txRemainingByteCount;
                    }
 
                    wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap);
                    handle->txData += handle->bytesEachWrite;
 
                    /*Decrease the remaining TX byte count.*/
                    handle->txRemainingByteCount -= handle->bytesEachWrite;
 
                    /*Write the word to TX register*/
                    LPSPI_WriteData(base, wordToSend);
                }
 
                if (handle->rxRemainingByteCount == 0)
                {
                    break;
                }
            }
        }
 
        /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there
         *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark.
         */
        if ((handle->readRegRemainingTimes) <= (handle->rxWatermark))
        {
            base->FCR =
                (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) |
                LPSPI_FCR_RXWATER((handle->readRegRemainingTimes > 1) ? (handle->readRegRemainingTimes - 1U) : (0U));
        }
    }
    else if ((handle->txRemainingByteCount) && (handle->txData != NULL))
    {
        LPSPI_SlaveTransferFillUpTxFifo(base, handle);
    }
    else
    {
        __NOP();
    }
 
    if ((handle->txRemainingByteCount == 0) && (handle->rxRemainingByteCount == 0))
    {
        /* If no RX buffer, then transfer is not complete until transfer complete flag sets and the TX FIFO empty*/
        if (handle->rxData == NULL)
        {
            if ((LPSPI_GetStatusFlags(base) & kLPSPI_FrameCompleteFlag) && (LPSPI_GetTxFifoCount(base) == 0))
            {
                /* Complete the transfer and disable the interrupts */
                LPSPI_SlaveTransferComplete(base, handle);
            }
            else
            {
                LPSPI_ClearStatusFlags(base, kLPSPI_FrameCompleteFlag);
                LPSPI_EnableInterrupts(base, kLPSPI_FrameCompleteInterruptEnable);
                LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable);
            }
        }
        else
        {
            /* Complete the transfer and disable the interrupts */
            LPSPI_SlaveTransferComplete(base, handle);
        }
    }
 
    /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */
    if ((LPSPI_GetStatusFlags(base) & kLPSPI_TransmitErrorFlag) && (base->IER & LPSPI_IER_TEIE_MASK))
    {
        LPSPI_ClearStatusFlags(base, kLPSPI_TransmitErrorFlag);
        /* Change state to error and clear flag */
        if (handle->txData)
        {
            handle->state = kLPSPI_Error;
        }
        handle->errorCount++;
    }
    /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */
    if ((LPSPI_GetStatusFlags(base) & kLPSPI_ReceiveErrorFlag) && (base->IER & LPSPI_IER_REIE_MASK))
    {
        LPSPI_ClearStatusFlags(base, kLPSPI_ReceiveErrorFlag);
        /* Change state to error and clear flag */
        if (handle->txData)
        {
            handle->state = kLPSPI_Error;
        }
        handle->errorCount++;
    }
}

Referenced by LPSPI_SlaveTransferCreateHandle().

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LPSPI_SlaveTransferNonBlocking()

status_t LPSPI_SlaveTransferNonBlocking	(	LPSPI_Type *	base,
		lpspi_slave_handle_t *	handle,
		lpspi_transfer_t *	transfer
	)

LPSPI slave transfer data using an interrupt method.

This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters

base	LPSPI peripheral address.
handle	pointer to lpspi_slave_handle_t structure which stores the transfer state.
transfer	pointer to lpspi_transfer_t structure.

Returns

status of status_t.

brief LPSPI slave transfer data using an interrupt method.

This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

param base LPSPI peripheral address. param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. param transfer pointer to lpspi_transfer_t structure. return status of status_t.

Definition at line 1403 of file fsl_lpspi.c.

{
    assert(handle);
    assert(transfer);
 
    uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
    uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8;
    uint32_t temp = 0U;
 
    if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame))
    {
        return kStatus_InvalidArgument;
    }
 
    /* Check that we're not busy.*/
    if (handle->state == kLPSPI_Busy)
    {
        return kStatus_LPSPI_Busy;
    }
    handle->state = kLPSPI_Busy;
 
    bool isRxMask = false;
    bool isTxMask = false;
 
    uint32_t whichPcs = (transfer->configFlags & LPSPI_SLAVE_PCS_MASK) >> LPSPI_SLAVE_PCS_SHIFT;
 
    handle->txData = transfer->txData;
    handle->rxData = transfer->rxData;
    handle->txRemainingByteCount = transfer->dataSize;
    handle->rxRemainingByteCount = transfer->dataSize;
    handle->totalByteCount = transfer->dataSize;
 
    handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4);
    handle->readRegRemainingTimes = handle->writeRegRemainingTimes;
 
    /*The TX and RX FIFO sizes are always the same*/
    handle->fifoSize = LPSPI_GetRxFifoSize(base);
 
    handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_SlaveByteSwap);
 
    /*Set the RX and TX watermarks to reduce the ISR times.*/
    uint8_t txWatermark;
    if (handle->fifoSize > 1)
    {
        txWatermark = 1;
        handle->rxWatermark = handle->fifoSize - 2;
    }
    else
    {
        txWatermark = 0;
        handle->rxWatermark = 0;
    }
    LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark);
 
    /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */
    temp = base->CFGR1;
    temp &= LPSPI_CFGR1_PINCFG_MASK;
    if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut)))
    {
        if (!handle->txData)
        {
            LPSPI_Enable(base, false);
            base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK;
            LPSPI_Enable(base, true);
        }
        /* The 3-wire mode can't send and receive data at the same time. */
        if ((handle->txData) && (handle->rxData))
        {
            return kStatus_InvalidArgument;
        }
    }
 
    /*Flush FIFO , clear status , disable all the inerrupts.*/
    LPSPI_FlushFifo(base, true, true);
    LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag);
    LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable);
 
    /*If there is not rxData , can mask the receive data (receive data is not stored in receive FIFO).*/
    if (handle->rxData == NULL)
    {
        isRxMask = true;
        handle->rxRemainingByteCount = 0;
    }
 
    /*If there is not txData , can mask the transmit data (no data is loaded from transmit FIFO and output pin
     * is tristated).
     */
    if (handle->txData == NULL)
    {
        isTxMask = true;
        handle->txRemainingByteCount = 0;
    }
 
    base->TCR = (base->TCR &
                 ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_TXMSK_MASK |
                   LPSPI_TCR_PCS_MASK)) |
                LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) |
                LPSPI_TCR_PCS(whichPcs);
 
    /*Calculate the bytes for write/read the TX/RX register each time*/
    if (bytesPerFrame <= 4)
    {
        handle->bytesEachWrite = bytesPerFrame;
        handle->bytesEachRead = bytesPerFrame;
    }
    else
    {
        handle->bytesEachWrite = 4;
        handle->bytesEachRead = 4;
    }
 
    /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX ,
     * and you should also enable the INTMUX interupt in your application.
     */
    EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]);
 
    /*TCR is also shared the FIFO , so wait for TCR written.*/
    while (LPSPI_GetTxFifoCount(base) != 0)
    {
    }
 
    /*Fill up the TX data in FIFO */
    if (handle->txData)
    {
        LPSPI_SlaveTransferFillUpTxFifo(base, handle);
    }
 
    /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data.
     * The IRQ handler will get the status of RX and TX interrupt flags.
     */
    if (handle->rxData)
    {
        /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there
         *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark.
         */
        if ((handle->readRegRemainingTimes) <= handle->rxWatermark)
        {
            base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->readRegRemainingTimes - 1);
        }
 
        LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable);
    }
    else
    {
        LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable);
    }
 
    if (handle->rxData)
    {
        /* RX FIFO overflow request enable */
        LPSPI_EnableInterrupts(base, kLPSPI_ReceiveErrorInterruptEnable);
    }
    if (handle->txData)
    {
        /* TX FIFO underflow request enable */
        LPSPI_EnableInterrupts(base, kLPSPI_TransmitErrorInterruptEnable);
    }
 
    return kStatus_Success;
}

Referenced by spi_lld_exchange(), spi_lld_receive(), and spi_lld_send().

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LPSPI_WriteData()

static void LPSPI_WriteData ( LPSPI_Type *  base, uint32_t  data  )

inlinestatic

Writes data into the transmit data buffer.

This function writes data passed in by the user to the Transmit Data Register (TDR). The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, the user has to manage sending the data one 32-bit word at a time. Any writes to the TDR result in an immediate push to the transmit FIFO. This function can be used for either master or slave modes.

Parameters

base	LPSPI peripheral address.
data	The data word to be sent.

Definition at line 904 of file fsl_lpspi.h.

{
    base->TDR = data;
}

Referenced by LPSPI_MasterTransferBlocking(), LPSPI_MasterTransferFillUpTxFifo(), LPSPI_SlaveTransferFillUpTxFifo(), and LPSPI_SlaveTransferHandleIRQ().

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Variable Documentation

g_lpspiDummyData

volatile uint8_t g_lpspiDummyData[]

extern

Global variable for dummy data value setting.

Definition at line 142 of file fsl_lpspi.c.

{0};

Referenced by LPSPI_MasterTransferBlocking(), LPSPI_MasterTransferEDMA(), LPSPI_MasterTransferNonBlocking(), LPSPI_SetDummyData(), and LPSPI_SlaveTransferEDMA().