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board.c
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1/**
2 * @file boards/f429-discovery/board.c
3 *
4 * @date Jan 08, 2022
5 * @author Andrey Gusakov, 2022
6 */
7
8#include "hal.h"
9#include "hal_community.h"
10#include "hal_sdram_lld.h"
11#include "unused.h"
12
13#include "board.h"
14
15/*
16 * SDRAM driver configuration structure.
17 */
18static const SDRAMConfig sdram_cfg = {
19 .sdcr = (uint32_t) (FMC_ColumnBits_Number_8b |
20 FMC_RowBits_Number_12b |
21 FMC_SDMemory_Width_16b |
22 FMC_InternalBank_Number_4 |
23 FMC_CAS_Latency_3 |
24 FMC_Write_Protection_Disable |
25 FMC_SDClock_Period_2 |
26 FMC_Read_Burst_Disable |
27 FMC_ReadPipe_Delay_1),
28
29 .sdtr = (uint32_t)( (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
30 (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
31 (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
32 (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns))
33 (2 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns))
34 (2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns)
35 (2 << 24)), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
36
37 .sdcmr = (uint32_t)(((4 - 1) << 5) |
38 ((FMC_SDCMR_MRD_BURST_LENGTH_2 |
39 FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
40 FMC_SDCMR_MRD_CAS_LATENCY_3 |
41 FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
42 FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9)),
43
44 /* if (STM32_SYSCLK == 180000000) ->
45 64ms / 4096 = 15.625us
46 15.625us * 90MHz = 1406 - 20 = 1386 */
47 //.sdrtr = (1386 << 1),
48 .sdrtr = (uint32_t)(683 << 1),
49};
50
51/*===========================================================================*/
52/* Driver local definitions. */
53/*===========================================================================*/
54
55/*===========================================================================*/
56/* Driver exported variables. */
57/*===========================================================================*/
58
59/*===========================================================================*/
60/* Driver local variables and types. */
61/*===========================================================================*/
62
63/**
64 * @brief Type of STM32 GPIO port setup.
65 */
66typedef struct {
67 uint32_t moder;
68 uint32_t otyper;
69 uint32_t ospeedr;
70 uint32_t pupdr;
71 uint32_t odr;
72 uint32_t afrl;
73 uint32_t afrh;
74} gpio_setup_t;
75
76/**
77 * @brief Type of STM32 GPIO initialization data.
78 */
79typedef struct {
80#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
81 gpio_setup_t PAData;
82#endif
83#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
84 gpio_setup_t PBData;
85#endif
86#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
87 gpio_setup_t PCData;
88#endif
89#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
90 gpio_setup_t PDData;
91#endif
92#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
93 gpio_setup_t PEData;
94#endif
95#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
96 gpio_setup_t PFData;
97#endif
98#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
99 gpio_setup_t PGData;
100#endif
101#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
102 gpio_setup_t PHData;
103#endif
104#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
105 gpio_setup_t PIData;
106#endif
107#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
108 gpio_setup_t PJData;
109#endif
110#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
111 gpio_setup_t PKData;
112#endif
113} gpio_config_t;
114
115/**
116 * @brief STM32 GPIO static initialization data.
117 */
118static const gpio_config_t gpio_default_config = {
119#if STM32_HAS_GPIOA
120 {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
121 VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
122#endif
123#if STM32_HAS_GPIOB
124 {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
125 VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
126#endif
127#if STM32_HAS_GPIOC
128 {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
129 VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
130#endif
131#if STM32_HAS_GPIOD
132 {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
133 VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
134#endif
135#if STM32_HAS_GPIOE
136 {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
137 VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
138#endif
139#if STM32_HAS_GPIOF
140 {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
141 VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
142#endif
143#if STM32_HAS_GPIOG
144 {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
145 VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
146#endif
147#if STM32_HAS_GPIOH
148 {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
149 VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
150#endif
151#if STM32_HAS_GPIOI
152 {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
153 VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
154#endif
155#if STM32_HAS_GPIOJ
156 {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
157 VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
158#endif
159#if STM32_HAS_GPIOK
160 {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
161 VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
162#endif
163};
164
165/*===========================================================================*/
166/* Driver local functions. */
167/*===========================================================================*/
168
169static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
170
171 gpiop->OTYPER = config->otyper;
172 gpiop->OSPEEDR = config->ospeedr;
173 gpiop->PUPDR = config->pupdr;
174 gpiop->ODR = config->odr;
175 gpiop->AFRL = config->afrl;
176 gpiop->AFRH = config->afrh;
177 gpiop->MODER = config->moder;
178}
179
180static void stm32_gpio_init(void) {
181
182 /* Enabling GPIO-related clocks, the mask comes from the
183 registry header file.*/
184 rccResetAHB1(STM32_GPIO_EN_MASK);
185 rccEnableAHB1(STM32_GPIO_EN_MASK, true);
186
187 /* Initializing all the defined GPIO ports.*/
188#if STM32_HAS_GPIOA
189 gpio_init(GPIOA, &gpio_default_config.PAData);
190#endif
191#if STM32_HAS_GPIOB
192 gpio_init(GPIOB, &gpio_default_config.PBData);
193#endif
194#if STM32_HAS_GPIOC
195 gpio_init(GPIOC, &gpio_default_config.PCData);
196#endif
197#if STM32_HAS_GPIOD
198 gpio_init(GPIOD, &gpio_default_config.PDData);
199#endif
200#if STM32_HAS_GPIOE
201 gpio_init(GPIOE, &gpio_default_config.PEData);
202#endif
203#if STM32_HAS_GPIOF
204 gpio_init(GPIOF, &gpio_default_config.PFData);
205#endif
206#if STM32_HAS_GPIOG
207 gpio_init(GPIOG, &gpio_default_config.PGData);
208#endif
209#if STM32_HAS_GPIOH
210 gpio_init(GPIOH, &gpio_default_config.PHData);
211#endif
212#if STM32_HAS_GPIOI
213 gpio_init(GPIOI, &gpio_default_config.PIData);
214#endif
215#if STM32_HAS_GPIOJ
216 gpio_init(GPIOJ, &gpio_default_config.PJData);
217#endif
218#if STM32_HAS_GPIOK
219 gpio_init(GPIOK, &gpio_default_config.PKData);
220#endif
221}
222
223/*===========================================================================*/
224/* Driver interrupt handlers. */
225/*===========================================================================*/
226
227/*===========================================================================*/
228/* Driver exported functions. */
229/*===========================================================================*/
230
231#define SDRAM ((FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE)
232
233/**
234 * FMC_Command_Mode
235 */
236#define FMCCM_NORMAL ((uint32_t)0x00000000)
237#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001)
238#define FMCCM_PALL ((uint32_t)0x00000002)
239#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003)
240#define FMCCM_LOAD_MODE ((uint32_t)0x00000004)
241#define FMCCM_SELFREFRESH ((uint32_t)0x00000005)
242#define FMCCM_POWER_DOWN ((uint32_t)0x00000006)
243
244static void __early_sdram_wait_ready(void) {
245 /* Wait until the SDRAM controller is ready */
246 while (SDRAM->SDSR & FMC_SDSR_BUSY);
247}
248
249static void __early_sdram_delay(void)
250{
251 /* something > 100uS */
252 volatile int tmp = 168 * 1000 * 100;
253
254 do {
255 tmp--;
256 } while(tmp);
257}
258
259static void __early_sdram_init(const SDRAMConfig *config)
260{
261 uint32_t command_target = 0;
262
263 #ifdef rccResetFSMC
264 rccResetFSMC();
265 #endif
266 rccEnableFSMC(FALSE);
267
268 SDRAM->SDCR1 = config->sdcr;
269 SDRAM->SDTR1 = config->sdtr;
270 SDRAM->SDCR2 = config->sdcr;
271 SDRAM->SDTR2 = config->sdtr;
272
273#if STM32_SDRAM_USE_SDRAM1
274 command_target |= FMC_SDCMR_CTB1;
275#endif
276#if STM32_SDRAM_USE_SDRAM2
277 command_target |= FMC_SDCMR_CTB2;
278#endif
279
280 /* Step 3: Configure a clock configuration enable command.*/
281 __early_sdram_wait_ready();
282 SDRAM->SDCMR = FMCCM_CLK_ENABLED | command_target;
283
284 /* Step 4: Insert delay (tipically 100uS).*/
285 __early_sdram_delay();
286
287 /* Step 5: Configure a PALL (precharge all) command.*/
288 __early_sdram_wait_ready();
289 SDRAM->SDCMR = FMCCM_PALL | command_target;
290
291 /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
292 __early_sdram_wait_ready();
293 SDRAM->SDCMR = FMCCM_AUTO_REFRESH | command_target |
294 (config->sdcmr & FMC_SDCMR_NRFS);
295
296 /* Step 6.2: Send the second command.*/
297 __early_sdram_wait_ready();
298 SDRAM->SDCMR = FMCCM_AUTO_REFRESH | command_target |
299 (config->sdcmr & FMC_SDCMR_NRFS);
300
301 /* Step 7: Program the external memory mode register.*/
302 __early_sdram_wait_ready();
303 SDRAM->SDCMR = FMCCM_LOAD_MODE | command_target |
304 (config->sdcmr & FMC_SDCMR_MRD);
305
306 /* Step 8: Set clock.*/
307 __early_sdram_wait_ready();
308 SDRAM->SDRTR = config->sdrtr & FMC_SDRTR_COUNT;
309
310 __early_sdram_wait_ready();
311}
312
313static int __early_sdram_test(void *base, size_t size)
314{
315 size_t i;
316 uint32_t *ptr = base;
317
318 /* test 0 */
319 for (i = 0; i < size / sizeof(uint32_t); i++) {
320 ptr[i] = 0;
321 }
322
323 for (i = 0; i < size / sizeof(uint32_t); i++) {
324 if (ptr[i] != 0)
325 return -1;
326 }
327
328 /* test 1 */
329 for (i = 0; i < size / sizeof(uint32_t); i++) {
330 ptr[i] = 0xffffffff;
331 }
332
333 for (i = 0; i < size / sizeof(uint32_t); i++) {
334 if (ptr[i] != 0xffffffff)
335 return -1;
336 }
337
338 /* test 2 */
339 for (i = 0; i < size / sizeof(uint32_t); i++) {
340 ptr[i] = i;
341 }
342
343 for (i = 0; i < size / sizeof(uint32_t); i++) {
344 if (ptr[i] != i)
345 return -1;
346 }
347
348 return 0;
349}
350
351/**
352 * @brief Early initialization code.
353 * @details GPIO ports and system clocks are initialized before everything
354 * else.
355 */
356void __early_init(void) {
357
358 stm32_gpio_init();
359 stm32_clock_init();
360
361 /*
362 * Initialise FSMC for SDRAM.
363 */
364#if 0
365 /* clear driver struct */
366 memset(&SDRAMD1, 0 sizeof(SDRAMD1));
367 sdramInit();
368 sdramStart(&SDRAMD1, &sdram_cfg);
369#else
370 __early_sdram_init(&sdram_cfg);
371#endif
372
373 if (0) {
374 /* yes, hardcoded values */
375 __early_sdram_test((void *) 0xD0000000, 8 * 1024 * 1024);
376 }
377}
378
379#if HAL_USE_SDC || defined(__DOXYGEN__)
380/**
381 * @brief SDC card detection.
382 */
383bool sdc_lld_is_card_inserted(SDCDriver *sdcp)
384{
385 UNUSED(sdcp);
386 /* TODO: Fill the implementation.*/
387 return true;
388}
389
390/**
391 * @brief SDC card write protection detection.
392 */
393bool sdc_lld_is_write_protected(SDCDriver *sdcp)
394{
395 UNUSED(sdcp);
396 /* TODO: Fill the implementation.*/
397 return false;
398}
399#endif /* HAL_USE_SDC */
400
401#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
402/**
403 * @brief MMC_SPI card detection.
404 */
405bool mmc_lld_is_card_inserted(MMCDriver *mmcp)
406{
407 UNUSED(mmcp);
408 /* TODO: Fill the implementation.*/
409 return true;
410}
411
412/**
413 * @brief MMC_SPI card write protection detection.
414 */
415bool mmc_lld_is_write_protected(MMCDriver *mmcp)
416{
417 UNUSED(mmcp);
418 /* TODO: Fill the implementation.*/
419 return false;
420}
421#endif
__early_init
void __early_init(void)
Definition board.c:21
config
static constexpr persistent_config_s * config
Definition engine_configuration.h:81
sdc_lld_is_write_protected
bool sdc_lld_is_write_protected(SDCDriver *sdcp)
SDC card write protection detection.
Definition board.c:394
mmc_lld_is_card_inserted
bool mmc_lld_is_card_inserted(MMCDriver *mmcp)
MMC_SPI card detection.
Definition board.c:406
mmc_lld_is_write_protected
bool mmc_lld_is_write_protected(MMCDriver *mmcp)
MMC_SPI card write protection detection.
Definition board.c:416
stm32_gpio_init
static void stm32_gpio_init(void)
Definition board.c:181
gpio_init
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config)
Definition board.c:170
gpio_default_config
static const gpio_config_t gpio_default_config
STM32 GPIO static initialization data.
Definition board.c:119
__early_sdram_delay
static void __early_sdram_delay(void)
Definition board.c:250
__early_sdram_init
static void __early_sdram_init(const SDRAMConfig *config)
Definition board.c:260
sdram_cfg
static const SDRAMConfig sdram_cfg
Definition board.c:19
__early_sdram_wait_ready
static void __early_sdram_wait_ready(void)
Definition board.c:245
__early_sdram_test
static int __early_sdram_test(void *base, size_t size)
Definition board.c:314
sdc_lld_is_card_inserted
bool sdc_lld_is_card_inserted(SDCDriver *sdcp)
SDC card detection.
Definition board.c:384
UNUSED
UNUSED(samplingTimeSeconds)
size
composite packet size
Definition tooth_logger.cpp:23
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