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hw_layer
ports
cypress
port_mpu_util.h
Go to the documentation of this file.
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/**
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* @file port_mpu_util.h
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*
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* @date Jul 27, 2014
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* @author Andrey Belomutskiy, (c) 2012-2020
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* @author andreika <prometheus.pcb@gmail.com>
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*/
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#pragma once
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#define PORT_SIZE 16
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// todo: stm32 ticks are based on 4MHz timer I wonder if these STM32_SYSCLK-based clocks are broken here?!
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#define US_TO_NT_MULTIPLIER (STM32_SYSCLK / 1000000)
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// Scheduler queue GPT device
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#define GPTDEVICE GPTD1
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typedef
enum
{
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BOR_Level_None
= 0,
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BOR_Level_1
= 1,
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BOR_Level_2
= 2,
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BOR_Level_3
= 3
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}
BOR_Level_t
;
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// we are lucky - all CAN pins use the same AF
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#define EFI_CAN_RX_AF 9
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#define EFI_CAN_TX_AF 9
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#ifndef ADC_TwoSamplingDelay_5Cycles
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#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)
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#endif
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#ifndef ADC_TwoSamplingDelay_20Cycles
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#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)
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#endif
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#ifndef ADC_CR2_SWSTART
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#define ADC_CR2_SWSTART ((uint32_t)0x40000000)
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#endif
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#define SPI_CR1_8BIT_MODE 0
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#define SPI_CR2_8BIT_MODE 0
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#define SPI_CR1_16BIT_MODE SPI_CR1_DFF
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#define SPI_CR2_16BIT_MODE 0
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// TODO
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#define SPI_CR1_24BIT_MODE 0
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#define SPI_CR2_24BIT_MODE 0
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#define ADC_MAX_VALUE 4095
BOR_Level_t
BOR_Level_t
Definition
port_mpu_util.h:19
BOR_Level_None
@ BOR_Level_None
Definition
port_mpu_util.h:20
BOR_Level_1
@ BOR_Level_1
Definition
port_mpu_util.h:21
BOR_Level_3
@ BOR_Level_3
Definition
port_mpu_util.h:23
BOR_Level_2
@ BOR_Level_2
Definition
port_mpu_util.h:22
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