rusEFI
The most advanced open source ECU
Loading...
Searching...
No Matches
pdl_user.h
Go to the documentation of this file.
1/*******************************************************************************
2* \file pdl_user.h
3*
4* \version 1.10
5*
6* \brief User settings headerfile for Peripheral Driver Library
7*
8********************************************************************************
9* \copyright
10* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved.
11* You may use this file only in accordance with the license, terms, conditions,
12* disclaimers, and limitations in the end user license agreement accompanying
13* the software package with which this file was provided.
14* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY
15* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE,
16* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
18* PURPOSE.
19*******************************************************************************/
20#ifndef __PDL_USER_H__
21#define __PDL_USER_H__
22
23#include "pdl.h"
24
25/******************************************************************************/
26/* Global pre-processor symbols/macros ('#define') */
27/******************************************************************************/
28
29/**
30 ******************************************************************************
31 ** User Defines for PDL resource activation
32 **
33 ** Possible definitions are PDL_ON and PDL_OFF.
34 **
35 ******************************************************************************/
36// ADC
37#define PDL_PERIPHERAL_ENABLE_ADC0 PDL_ON
38#define PDL_PERIPHERAL_ENABLE_ADC1 PDL_ON
39#define PDL_PERIPHERAL_ENABLE_ADC2 PDL_ON
40
41// AES
42#define PDL_PERIPHERAL_ENABLE_AES PDL_OFF
43
44// Base Timers
45#define PDL_PERIPHERAL_ENABLE_BT0 PDL_ON
46#define PDL_PERIPHERAL_ENABLE_BT1 PDL_ON
47#define PDL_PERIPHERAL_ENABLE_BT2 PDL_ON
48#define PDL_PERIPHERAL_ENABLE_BT3 PDL_ON
49#define PDL_PERIPHERAL_ENABLE_BT4 PDL_OFF
50#define PDL_PERIPHERAL_ENABLE_BT5 PDL_OFF
51#define PDL_PERIPHERAL_ENABLE_BT6 PDL_OFF
52#define PDL_PERIPHERAL_ENABLE_BT7 PDL_OFF
53#define PDL_PERIPHERAL_ENABLE_BT8 PDL_OFF
54#define PDL_PERIPHERAL_ENABLE_BT9 PDL_OFF
55#define PDL_PERIPHERAL_ENABLE_BT10 PDL_OFF
56#define PDL_PERIPHERAL_ENABLE_BT11 PDL_OFF
57#define PDL_PERIPHERAL_ENABLE_BT12 PDL_OFF
58#define PDL_PERIPHERAL_ENABLE_BT13 PDL_OFF
59#define PDL_PERIPHERAL_ENABLE_BT14 PDL_OFF
60#define PDL_PERIPHERAL_ENABLE_BT15 PDL_OFF
61
62// Modes of Base Timers
63#define PDL_PERIPHERAL_ENABLE_BT_PWM_MODE PDL_OFF
64#define PDL_PERIPHERAL_ENABLE_BT_PPG_MODE PDL_OFF
65#define PDL_PERIPHERAL_ENABLE_BT_RT_MODE PDL_ON
66#define PDL_PERIPHERAL_ENABLE_BT_PWC_MODE PDL_OFF
67
68// CAN
69#define PDL_PERIPHERAL_ENABLE_CAN0 PDL_OFF
70#define PDL_PERIPHERAL_ENABLE_CAN1 PDL_OFF
71
72// CAN-FD
73#define PDL_PERIPHERAL_ENABLE_CANFD0 PDL_ON
74#define PDL_PERIPHERAL_ENABLE_CANFD1 PDL_OFF
75
76// Clock
77#define PDL_PERIPHERAL_ENABLE_CLK PDL_ON
78
79// CR Trimming
80#define PDL_PERIPHERAL_ENABLE_CR PDL_OFF
81
82// CRC
83#define PDL_PERIPHERAL_ENABLE_CRC0 PDL_OFF
84
85// Clock Supervisor
86#define PDL_PERIPHERAL_ENABLE_CSV PDL_OFF
87
88// DAC
89#define PDL_PERIPHERAL_ENABLE_DAC0 PDL_OFF
90
91// DMA
92#define PDL_PERIPHERAL_ENABLE_DMA0 PDL_ON
93#define PDL_PERIPHERAL_ENABLE_DMA1 PDL_OFF
94#define PDL_PERIPHERAL_ENABLE_DMA2 PDL_OFF
95#define PDL_PERIPHERAL_ENABLE_DMA3 PDL_OFF
96#define PDL_PERIPHERAL_ENABLE_DMA4 PDL_OFF
97#define PDL_PERIPHERAL_ENABLE_DMA5 PDL_OFF
98#define PDL_PERIPHERAL_ENABLE_DMA6 PDL_OFF
99#define PDL_PERIPHERAL_ENABLE_DMA7 PDL_OFF
100
101// DSTC
102#define PDL_PERIPHERAL_ENABLE_DSTC PDL_OFF
103
104// Dual Timer(s)
105#define PDL_PERIPHERAL_ENABLE_DT0 PDL_OFF
106
107// Ethernet
108// Please activate/deactivate in emac_user.h
109
110// External Interrupts
111#define PDL_PERIPHERAL_ENABLE_EXINT0 PDL_OFF
112#define PDL_PERIPHERAL_ENABLE_EXINT1 PDL_OFF
113#define PDL_PERIPHERAL_ENABLE_EXINT2 PDL_OFF
114#define PDL_PERIPHERAL_ENABLE_EXINT3 PDL_OFF
115#define PDL_PERIPHERAL_ENABLE_EXINT4 PDL_OFF
116#define PDL_PERIPHERAL_ENABLE_EXINT5 PDL_OFF
117#define PDL_PERIPHERAL_ENABLE_EXINT6 PDL_OFF
118#define PDL_PERIPHERAL_ENABLE_EXINT7 PDL_OFF
119#define PDL_PERIPHERAL_ENABLE_EXINT8 PDL_ON // P10 crank
120#define PDL_PERIPHERAL_ENABLE_EXINT9 PDL_ON // P29 res_in
121#define PDL_PERIPHERAL_ENABLE_EXINT10 PDL_ON // P18 cam
122#define PDL_PERIPHERAL_ENABLE_EXINT11 PDL_ON // P1B aux1
123#define PDL_PERIPHERAL_ENABLE_EXINT12 PDL_OFF
124#define PDL_PERIPHERAL_ENABLE_EXINT13 PDL_ON // PC7 res2
125#define PDL_PERIPHERAL_ENABLE_EXINT14 PDL_OFF
126#define PDL_PERIPHERAL_ENABLE_EXINT15 PDL_OFF
127#define PDL_PERIPHERAL_ENABLE_EXINT16 PDL_OFF
128#define PDL_PERIPHERAL_ENABLE_EXINT17 PDL_OFF
129#define PDL_PERIPHERAL_ENABLE_EXINT18 PDL_OFF
130#define PDL_PERIPHERAL_ENABLE_EXINT19 PDL_ON // P32 drv_miso
131#define PDL_PERIPHERAL_ENABLE_EXINT20 PDL_OFF
132#define PDL_PERIPHERAL_ENABLE_EXINT21 PDL_OFF
133#define PDL_PERIPHERAL_ENABLE_EXINT22 PDL_OFF
134#define PDL_PERIPHERAL_ENABLE_EXINT23 PDL_OFF
135#define PDL_PERIPHERAL_ENABLE_EXINT24 PDL_ON // P19 vss
136#define PDL_PERIPHERAL_ENABLE_EXINT25 PDL_ON // P25 aux4
137#define PDL_PERIPHERAL_ENABLE_EXINT26 PDL_ON // P1E aux2
138#define PDL_PERIPHERAL_ENABLE_EXINT27 PDL_ON // P1F aux3
139#define PDL_PERIPHERAL_ENABLE_EXINT28 PDL_OFF
140#define PDL_PERIPHERAL_ENABLE_EXINT29 PDL_OFF
141#define PDL_PERIPHERAL_ENABLE_EXINT30 PDL_OFF
142#define PDL_PERIPHERAL_ENABLE_EXINT31 PDL_ON // P60 vbus_det
143
144// External Bus Interface
145#define PDL_PERIPHERAL_ENABLE_EXTIF PDL_OFF
146
147// Flash routines
148#define PDL_PERIPHERAL_ENABLE_MAIN_FLASH PDL_ON
149#define PDL_PERIPHERAL_ENABLE_DUAL_FLASH PDL_ON
150#define PDL_PERIPHERAL_ENABLE_WORK_FLASH PDL_OFF
151
152// GPIO header inclusion
153#define PDL_PERIPHERAL_ENABLE_GPIO PDL_ON
154
155// Hyber Bus Interface
156#define PDL_PERIPHERAL_ENABLE_HBIF PDL_OFF
157
158// High-Speed Quad SPI
159#define PDL_PERIPHERAL_ENABLE_HSSPI0 PDL_OFF
160
161// I2C Slave
162#define PDL_PERIPHERAL_ENABLE_I2CS0 PDL_OFF
163
164// ICC
165#define PDL_PERIPHERAL_ENABLE_ICC0 PDL_OFF
166#define PDL_PERIPHERAL_ENABLE_ICC1 PDL_OFF
167
168// I2S
169#define PDL_PERIPHERAL_ENABLE_I2S0 PDL_OFF
170#define PDL_PERIPHERAL_ENABLE_I2S1 PDL_OFF
171
172// I2S-Lite
173#define PDL_PERIPHERAL_ENABLE_I2SL0 PDL_OFF
174#define PDL_PERIPHERAL_ENABLE_I2SL1 PDL_OFF
175
176// LCD controller
177#define PDL_PERIPHERAL_ENABLE_LCD PDL_OFF
178
179// LPM
180#define PDL_PERIPHERAL_ENABLE_LPM PDL_OFF
181
182// Low Voltage Detection
183#define PDL_PERIPHERAL_ENABLE_LVD PDL_OFF
184
185// Multi Function Serial Interfaces
186#define PDL_PERIPHERAL_ENABLE_MFS0 PDL_ON
187#define PDL_PERIPHERAL_ENABLE_MFS1 PDL_OFF
188#define PDL_PERIPHERAL_ENABLE_MFS2 PDL_OFF
189#define PDL_PERIPHERAL_ENABLE_MFS3 PDL_ON
190#define PDL_PERIPHERAL_ENABLE_MFS4 PDL_OFF
191#define PDL_PERIPHERAL_ENABLE_MFS5 PDL_OFF
192#define PDL_PERIPHERAL_ENABLE_MFS6 PDL_ON
193#define PDL_PERIPHERAL_ENABLE_MFS7 PDL_ON
194#define PDL_PERIPHERAL_ENABLE_MFS8 PDL_OFF
195#define PDL_PERIPHERAL_ENABLE_MFS9 PDL_OFF
196#define PDL_PERIPHERAL_ENABLE_MFS10 PDL_OFF
197#define PDL_PERIPHERAL_ENABLE_MFS11 PDL_OFF
198#define PDL_PERIPHERAL_ENABLE_MFS12 PDL_OFF
199#define PDL_PERIPHERAL_ENABLE_MFS13 PDL_OFF
200#define PDL_PERIPHERAL_ENABLE_MFS14 PDL_OFF
201#define PDL_PERIPHERAL_ENABLE_MFS15 PDL_OFF
202
203// Modes of Multi Function Serial Interfaces
204#define PDL_PERIPHERAL_ENABLE_MFS_UART_MODE PDL_ON
205#define PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE PDL_ON
206#define PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE PDL_ON
207#define PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE PDL_ON
208
209// Multi Function Timer Interfaces
210#define PDL_PERIPHERAL_ENABLE_MFT0_FRT PDL_OFF
211#define PDL_PERIPHERAL_ENABLE_MFT0_OCU PDL_OFF
212#define PDL_PERIPHERAL_ENABLE_MFT0_WFG PDL_OFF
213#define PDL_PERIPHERAL_ENABLE_MFT0_ICU PDL_OFF
214#define PDL_PERIPHERAL_ENABLE_MFT0_ADCMP PDL_OFF
215
216#define PDL_PERIPHERAL_ENABLE_MFT1_FRT PDL_OFF
217#define PDL_PERIPHERAL_ENABLE_MFT1_OCU PDL_OFF
218#define PDL_PERIPHERAL_ENABLE_MFT1_WFG PDL_OFF
219#define PDL_PERIPHERAL_ENABLE_MFT1_ICU PDL_OFF
220#define PDL_PERIPHERAL_ENABLE_MFT1_ADCMP PDL_OFF
221
222#define PDL_PERIPHERAL_ENABLE_MFT2_FRT PDL_OFF
223#define PDL_PERIPHERAL_ENABLE_MFT2_OCU PDL_OFF
224#define PDL_PERIPHERAL_ENABLE_MFT2_WFG PDL_OFF
225#define PDL_PERIPHERAL_ENABLE_MFT2_ICU PDL_OFF
226#define PDL_PERIPHERAL_ENABLE_MFT2_ADCMP PDL_OFF
227
228// PPG
229#define PDL_PERIPHERAL_ENABLE_PPG PDL_OFF
230
231// Programmable-CRC
232#define PDL_PERIPHERAL_ENABLE_PCRC PDL_OFF
233
234// NMI
235#define PDL_PERIPHERAL_ENABLE_NMI PDL_OFF
236
237// Quad Decoder
238#define PDL_PERIPHERAL_ENABLE_QPRC0 PDL_OFF
239#define PDL_PERIPHERAL_ENABLE_QPRC1 PDL_OFF
240#define PDL_PERIPHERAL_ENABLE_QPRC2 PDL_OFF
241#define PDL_PERIPHERAL_ENABLE_QPRC3 PDL_OFF
242
243// Remote Control routines
244#define PDL_PERIPHERAL_ENABLE_RC0 PDL_OFF
245#define PDL_PERIPHERAL_ENABLE_RC1 PDL_OFF
246
247// RX modes of Remote Control routines
248#define PDL_PERIPHERAL_ENABLE_RCRX_SIRCS_MODE PDL_OFF
249#define PDL_PERIPHERAL_ENABLE_RCRX_NEC_MODE PDL_OFF
250#define PDL_PERIPHERAL_ENABLE_RCRX_CEC_MODE PDL_OFF
251
252// TX modes of Remote Control routines
253#define PDL_PERIPHERAL_ENABLE_RCTX_CEC_MODE PDL_OFF
254
255// Reset Cause
256#define PDL_PERIPHERAL_ENABLE_RESET PDL_OFF
257
258// Real Time Clock
259#define PDL_PERIPHERAL_ENABLE_RTC0 PDL_OFF
260
261// SD
262#define PDL_PERIPHERAL_ENABLE_SD0 PDL_OFF
263
264// Unique ID
265#define PDL_PERIPHERAL_ENABLE_UID PDL_OFF
266
267// USB
268#define PDL_PERIPHERAL_USB_ACTIVE PDL_ON
269#define PDL_PERIPHERAL_ENABLE_USB0_DEVICE PDL_ON
270#define PDL_PERIPHERAL_ENABLE_USB0_HOST PDL_OFF
271#define PDL_PERIPHERAL_ENABLE_USB1_DEVICE PDL_OFF
272#define PDL_PERIPHERAL_ENABLE_USB1_HOST PDL_OFF
273
274// USB Device Middle Ware
275#define PDL_USBDEVICECDCCOM_ENABLED PDL_ON
276#define PDL_USBDEVICEHIDCOM_ENABLED PDL_OFF
277#define PDL_USBDEVICEHIDJOYSTICK_ENABLED PDL_OFF
278#define PDL_USBDEVICEHIDKEYBOARD_ENABLED PDL_OFF
279#define PDL_USBDEVICEHIDMOUSE_ENABLED PDL_OFF
280#define PDL_USBDEVICELIBUSB_ENABLED PDL_OFF
281#define PDL_USBDEVICEPRINTER_ENABLED PDL_OFF
282
283// USB Host Middle Ware
284#define PDL_USBHOSTHIDCOM_ENABLED PDL_OFF
285#define PDL_USBHOSTHIDKEYBOARD_ENABLED PDL_OFF
286#define PDL_USBHOSTHIDMOUSE_ENABLED PDL_OFF
287#define PDL_USBHOSTMASSSTORAGE_ENABLED PDL_OFF
288
289// VBAT domain
290#define PDL_PERIPHERAL_ENABLE_VBAT PDL_OFF
291
292// Watch Counter
293#define PDL_PERIPHERAL_ENABLE_WC0 PDL_OFF
294
295// Watchdog Timers
296#define PDL_PERIPHERAL_ENABLE_HWWDG PDL_OFF
297#define PDL_PERIPHERAL_ENABLE_SWWDG PDL_OFF
298
299/**
300 ******************************************************************************
301 ** User Interrupt activation settings
302 **
303 ** Possible values are PDL_INT_ACTIVE (Interrupts active) and PDL_INT_INACTIVE
304 ** (Interrupts deactivated)
305 ******************************************************************************/
306// ADC
307#define PDL_INTERRUPT_ENABLE_ADC0 PDL_ON
308#define PDL_INTERRUPT_ENABLE_ADC1 PDL_ON
309#define PDL_INTERRUPT_ENABLE_ADC2 PDL_ON
310
311// Base Timers
312#define PDL_INTERRUPT_ENABLE_BT0 PDL_ON
313#define PDL_INTERRUPT_ENABLE_BT1 PDL_ON
314#define PDL_INTERRUPT_ENABLE_BT2 PDL_ON
315#define PDL_INTERRUPT_ENABLE_BT3 PDL_ON
316#define PDL_INTERRUPT_ENABLE_BT4 PDL_OFF
317#define PDL_INTERRUPT_ENABLE_BT5 PDL_OFF
318#define PDL_INTERRUPT_ENABLE_BT6 PDL_OFF
319#define PDL_INTERRUPT_ENABLE_BT7 PDL_OFF
320#define PDL_INTERRUPT_ENABLE_BT8 PDL_OFF
321#define PDL_INTERRUPT_ENABLE_BT9 PDL_OFF
322#define PDL_INTERRUPT_ENABLE_BT10 PDL_OFF
323#define PDL_INTERRUPT_ENABLE_BT11 PDL_OFF
324#define PDL_INTERRUPT_ENABLE_BT12 PDL_OFF
325#define PDL_INTERRUPT_ENABLE_BT13 PDL_OFF
326#define PDL_INTERRUPT_ENABLE_BT14 PDL_OFF
327#define PDL_INTERRUPT_ENABLE_BT15 PDL_OFF
328
329// CAN
330#define PDL_INTERRUPT_ENABLE_CAN0 PDL_OFF
331#define PDL_INTERRUPT_ENABLE_CAN1 PDL_OFF
332
333// CAN-FD
334#define PDL_INTERRUPT_ENABLE_CANFD0 PDL_ON
335#define PDL_INTERRUPT_ENABLE_CANFD1 PDL_OFF
336
337// Clock
338#define PDL_INTERRUPT_ENABLE_CLK PDL_OFF
339
340// Clock Supervisor
341#define PDL_INTERRUPT_ENABLE_CSV PDL_OFF
342
343// DMA
344#define PDL_INTERRUPT_ENABLE_DMA0 PDL_OFF
345#define PDL_INTERRUPT_ENABLE_DMA1 PDL_OFF
346#define PDL_INTERRUPT_ENABLE_DMA2 PDL_OFF
347#define PDL_INTERRUPT_ENABLE_DMA3 PDL_OFF
348#define PDL_INTERRUPT_ENABLE_DMA4 PDL_OFF
349#define PDL_INTERRUPT_ENABLE_DMA5 PDL_OFF
350#define PDL_INTERRUPT_ENABLE_DMA6 PDL_OFF
351#define PDL_INTERRUPT_ENABLE_DMA7 PDL_OFF
352
353// Dual Timer(s)
354#define PDL_INTERRUPT_ENABLE_DT0 PDL_OFF
355
356// DSTC
357#define PDL_INTERRUPT_ENABLE_DSTC PDL_OFF
358
359// External Interrupts (automatically set by peripheral enable)
360#if (PDL_PERIPHERAL_ENABLE_EXINT0 == PDL_ON)
361#define PDL_INTERRUPT_ENABLE_EXINT0 PDL_ON
362#else
363#define PDL_INTERRUPT_ENABLE_EXINT0 PDL_OFF
364#endif
365#if (PDL_PERIPHERAL_ENABLE_EXINT1 == PDL_ON)
366#define PDL_INTERRUPT_ENABLE_EXINT1 PDL_ON
367#else
368#define PDL_INTERRUPT_ENABLE_EXINT1 PDL_OFF
369#endif
370#if (PDL_PERIPHERAL_ENABLE_EXINT2 == PDL_ON)
371#define PDL_INTERRUPT_ENABLE_EXINT2 PDL_ON
372#else
373#define PDL_INTERRUPT_ENABLE_EXINT2 PDL_OFF
374#endif
375#if (PDL_PERIPHERAL_ENABLE_EXINT3 == PDL_ON)
376#define PDL_INTERRUPT_ENABLE_EXINT3 PDL_ON
377#else
378#define PDL_INTERRUPT_ENABLE_EXINT3 PDL_OFF
379#endif
380#if (PDL_PERIPHERAL_ENABLE_EXINT4 == PDL_ON)
381#define PDL_INTERRUPT_ENABLE_EXINT4 PDL_ON
382#else
383#define PDL_INTERRUPT_ENABLE_EXINT4 PDL_OFF
384#endif
385#if (PDL_PERIPHERAL_ENABLE_EXINT5 == PDL_ON)
386#define PDL_INTERRUPT_ENABLE_EXINT5 PDL_ON
387#else
388#define PDL_INTERRUPT_ENABLE_EXINT5 PDL_OFF
389#endif
390#if (PDL_PERIPHERAL_ENABLE_EXINT6 == PDL_ON)
391#define PDL_INTERRUPT_ENABLE_EXINT6 PDL_ON
392#else
393#define PDL_INTERRUPT_ENABLE_EXINT6 PDL_OFF
394#endif
395#if (PDL_PERIPHERAL_ENABLE_EXINT7 == PDL_ON)
396#define PDL_INTERRUPT_ENABLE_EXINT7 PDL_ON
397#else
398#define PDL_INTERRUPT_ENABLE_EXINT7 PDL_OFF
399#endif
400#if (PDL_PERIPHERAL_ENABLE_EXINT8 == PDL_ON)
401#define PDL_INTERRUPT_ENABLE_EXINT8 PDL_ON
402#else
403#define PDL_INTERRUPT_ENABLE_EXINT8 PDL_OFF
404#endif
405#if (PDL_PERIPHERAL_ENABLE_EXINT9 == PDL_ON)
406#define PDL_INTERRUPT_ENABLE_EXINT9 PDL_ON
407#else
408#define PDL_INTERRUPT_ENABLE_EXINT9 PDL_OFF
409#endif
410#if (PDL_PERIPHERAL_ENABLE_EXINT10 == PDL_ON)
411#define PDL_INTERRUPT_ENABLE_EXINT10 PDL_ON
412#else
413#define PDL_INTERRUPT_ENABLE_EXINT10 PDL_OFF
414#endif
415#if (PDL_PERIPHERAL_ENABLE_EXINT11 == PDL_ON)
416#define PDL_INTERRUPT_ENABLE_EXINT11 PDL_ON
417#else
418#define PDL_INTERRUPT_ENABLE_EXINT11 PDL_OFF
419#endif
420#if (PDL_PERIPHERAL_ENABLE_EXINT12 == PDL_ON)
421#define PDL_INTERRUPT_ENABLE_EXINT12 PDL_ON
422#else
423#define PDL_INTERRUPT_ENABLE_EXINT12 PDL_OFF
424#endif
425#if (PDL_PERIPHERAL_ENABLE_EXINT13 == PDL_ON)
426#define PDL_INTERRUPT_ENABLE_EXINT13 PDL_ON
427#else
428#define PDL_INTERRUPT_ENABLE_EXINT13 PDL_OFF
429#endif
430#if (PDL_PERIPHERAL_ENABLE_EXINT14 == PDL_ON)
431#define PDL_INTERRUPT_ENABLE_EXINT14 PDL_ON
432#else
433#define PDL_INTERRUPT_ENABLE_EXINT14 PDL_OFF
434#endif
435#if (PDL_PERIPHERAL_ENABLE_EXINT15 == PDL_ON)
436#define PDL_INTERRUPT_ENABLE_EXINT15 PDL_ON
437#else
438#define PDL_INTERRUPT_ENABLE_EXINT15 PDL_OFF
439#endif
440#if (PDL_PERIPHERAL_ENABLE_EXINT16== PDL_ON)
441#define PDL_INTERRUPT_ENABLE_EXINT16 PDL_ON
442#else
443#define PDL_INTERRUPT_ENABLE_EXINT16 PDL_OFF
444#endif
445#if (PDL_PERIPHERAL_ENABLE_EXINT17 == PDL_ON)
446#define PDL_INTERRUPT_ENABLE_EXINT17 PDL_ON
447#else
448#define PDL_INTERRUPT_ENABLE_EXINT17 PDL_OFF
449#endif
450#if (PDL_PERIPHERAL_ENABLE_EXINT18 == PDL_ON)
451#define PDL_INTERRUPT_ENABLE_EXINT18 PDL_ON
452#else
453#define PDL_INTERRUPT_ENABLE_EXINT18 PDL_OFF
454#endif
455#if (PDL_PERIPHERAL_ENABLE_EXINT19 == PDL_ON)
456#define PDL_INTERRUPT_ENABLE_EXINT19 PDL_ON
457#else
458#define PDL_INTERRUPT_ENABLE_EXINT19 PDL_OFF
459#endif
460#if (PDL_PERIPHERAL_ENABLE_EXINT20 == PDL_ON)
461#define PDL_INTERRUPT_ENABLE_EXINT20 PDL_ON
462#else
463#define PDL_INTERRUPT_ENABLE_EXINT20 PDL_OFF
464#endif
465#if (PDL_PERIPHERAL_ENABLE_EXINT21 == PDL_ON)
466#define PDL_INTERRUPT_ENABLE_EXINT21 PDL_ON
467#else
468#define PDL_INTERRUPT_ENABLE_EXINT21 PDL_OFF
469#endif
470#if (PDL_PERIPHERAL_ENABLE_EXINT22 == PDL_ON)
471#define PDL_INTERRUPT_ENABLE_EXINT22 PDL_ON
472#else
473#define PDL_INTERRUPT_ENABLE_EXINT22 PDL_OFF
474#endif
475#if (PDL_PERIPHERAL_ENABLE_EXINT23 == PDL_ON)
476#define PDL_INTERRUPT_ENABLE_EXINT23 PDL_ON
477#else
478#define PDL_INTERRUPT_ENABLE_EXINT23 PDL_OFF
479#endif
480#if (PDL_PERIPHERAL_ENABLE_EXINT24 == PDL_ON)
481#define PDL_INTERRUPT_ENABLE_EXINT24 PDL_ON
482#else
483#define PDL_INTERRUPT_ENABLE_EXINT24 PDL_OFF
484#endif
485#if (PDL_PERIPHERAL_ENABLE_EXINT25 == PDL_ON)
486#define PDL_INTERRUPT_ENABLE_EXINT25 PDL_ON
487#else
488#define PDL_INTERRUPT_ENABLE_EXINT25 PDL_OFF
489#endif
490#if (PDL_PERIPHERAL_ENABLE_EXINT26 == PDL_ON)
491#define PDL_INTERRUPT_ENABLE_EXINT26 PDL_ON
492#else
493#define PDL_INTERRUPT_ENABLE_EXINT26 PDL_OFF
494#endif
495#if (PDL_PERIPHERAL_ENABLE_EXINT27 == PDL_ON)
496#define PDL_INTERRUPT_ENABLE_EXINT27 PDL_ON
497#else
498#define PDL_INTERRUPT_ENABLE_EXINT27 PDL_OFF
499#endif
500#if (PDL_PERIPHERAL_ENABLE_EXINT28 == PDL_ON)
501#define PDL_INTERRUPT_ENABLE_EXINT28 PDL_ON
502#else
503#define PDL_INTERRUPT_ENABLE_EXINT28 PDL_OFF
504#endif
505#if (PDL_PERIPHERAL_ENABLE_EXINT29 == PDL_ON)
506#define PDL_INTERRUPT_ENABLE_EXINT29 PDL_ON
507#else
508#define PDL_INTERRUPT_ENABLE_EXINT29 PDL_OFF
509#endif
510#if (PDL_PERIPHERAL_ENABLE_EXINT30 == PDL_ON)
511#define PDL_INTERRUPT_ENABLE_EXINT30 PDL_ON
512#else
513#define PDL_INTERRUPT_ENABLE_EXINT30 PDL_OFF
514#endif
515#if (PDL_PERIPHERAL_ENABLE_EXINT31 == PDL_ON)
516#define PDL_INTERRUPT_ENABLE_EXINT31 PDL_ON
517#else
518#define PDL_INTERRUPT_ENABLE_EXINT31 PDL_OFF
519#endif
520
521// External Bus Interface
522#define PDL_INTERRUPT_ENABLE_EXTIF PDL_OFF
523
524// Flash
525#define PDL_INTERRUPT_ENABLE_FLASH PDL_ON
526
527// Hyper Bus Interface
528#define PDL_INTERRUPT_ENABLE_HBIF PDL_OFF
529
530// High-Speed Quad SPI
531#define PDL_INTERRUPT_ENABLE_HSSPI0 PDL_OFF
532
533// I2C Slave
534#define PDL_INTERRUPT_ENABLE_I2CS0 PDL_OFF
535
536// ICC
537#define PDL_INTERRUPT_ENABLE_ICC0 PDL_OFF
538#define PDL_INTERRUPT_ENABLE_ICC1 PDL_OFF
539
540// LCD
541#define PDL_INTERRUPT_ENABLE_LCD PDL_OFF
542
543// Low Voltage Detection
544#define PDL_INTERRUPT_ENABLE_LVD PDL_OFF
545
546// I2S
547#define PDL_INTERRUPT_ENABLE_I2S0 PDL_OFF
548#define PDL_INTERRUPT_ENABLE_I2S1 PDL_OFF
549
550// I2S-Lite
551#define PDL_INTERRUPT_ENABLE_I2SL0 PDL_OFF
552#define PDL_INTERRUPT_ENABLE_I2SL1 PDL_OFF
553
554// Multi Function Serial Interfaces
555#define PDL_INTERRUPT_ENABLE_MFS0 PDL_ON
556#define PDL_INTERRUPT_ENABLE_MFS1 PDL_OFF
557#define PDL_INTERRUPT_ENABLE_MFS2 PDL_OFF
558#define PDL_INTERRUPT_ENABLE_MFS3 PDL_ON
559#define PDL_INTERRUPT_ENABLE_MFS4 PDL_OFF
560#define PDL_INTERRUPT_ENABLE_MFS5 PDL_OFF
561#define PDL_INTERRUPT_ENABLE_MFS6 PDL_ON
562#define PDL_INTERRUPT_ENABLE_MFS7 PDL_ON
563#define PDL_INTERRUPT_ENABLE_MFS8 PDL_OFF
564#define PDL_INTERRUPT_ENABLE_MFS9 PDL_OFF
565#define PDL_INTERRUPT_ENABLE_MFS10 PDL_OFF
566#define PDL_INTERRUPT_ENABLE_MFS11 PDL_OFF
567#define PDL_INTERRUPT_ENABLE_MFS12 PDL_OFF
568#define PDL_INTERRUPT_ENABLE_MFS13 PDL_OFF
569#define PDL_INTERRUPT_ENABLE_MFS14 PDL_OFF
570#define PDL_INTERRUPT_ENABLE_MFS15 PDL_OFF
571
572// Multi Function Timer Interfaces
573#define PDL_INTERRUPT_ENABLE_MFT0_FRT PDL_OFF
574#define PDL_INTERRUPT_ENABLE_MFT0_OCU PDL_OFF
575#define PDL_INTERRUPT_ENABLE_MFT0_WFG PDL_OFF
576#define PDL_INTERRUPT_ENABLE_MFT0_ICU PDL_OFF
577
578#define PDL_INTERRUPT_ENABLE_MFT1_FRT PDL_OFF
579#define PDL_INTERRUPT_ENABLE_MFT1_OCU PDL_OFF
580#define PDL_INTERRUPT_ENABLE_MFT1_WFG PDL_OFF
581#define PDL_INTERRUPT_ENABLE_MFT1_ICU PDL_OFF
582
583#define PDL_INTERRUPT_ENABLE_MFT2_FRT PDL_OFF
584#define PDL_INTERRUPT_ENABLE_MFT2_OCU PDL_OFF
585#define PDL_INTERRUPT_ENABLE_MFT2_WFG PDL_OFF
586#define PDL_INTERRUPT_ENABLE_MFT2_ICU PDL_OFF
587
588// NMI
589#if (PDL_PERIPHERAL_ENABLE_NMI== PDL_ON)
590#define PDL_INTERRUPT_ENABLE_NMI PDL_ON
591#else
592#define PDL_INTERRUPT_ENABLE_NMI PDL_OFF
593#endif
594
595// Programmable-CRC
596#define PDL_INTERRUPT_ENABLE_PCRC PDL_OFF
597
598// PPG
599#define PDL_INTERRUPT_ENABLE_PPG PDL_OFF
600
601// Quad Decoder
602#define PDL_INTERRUPT_ENABLE_QPRC0 PDL_OFF
603#define PDL_INTERRUPT_ENABLE_QPRC1 PDL_OFF
604#define PDL_INTERRUPT_ENABLE_QPRC2 PDL_OFF
605#define PDL_INTERRUPT_ENABLE_QPRC3 PDL_OFF
606
607// Real Time Clock
608#define PDL_INTERRUPT_ENABLE_RTC0 PDL_OFF
609
610// Remote Control routines
611#define PDL_INTERRUPT_ENABLE_RC0 PDL_OFF
612#define PDL_INTERRUPT_ENABLE_RC1 PDL_OFF
613
614// SD Host
615#define PDL_INTERRUPT_ENABLE_SD0 PDL_OFF
616
617// USB
618#define PDL_INTERRUPT_ENABLE_USB0_DEVICE PDL_ON
619#define PDL_INTERRUPT_ENABLE_USB0_HOST PDL_OFF
620#define PDL_INTERRUPT_ENABLE_USB1_DEVICE PDL_OFF
621#define PDL_INTERRUPT_ENABLE_USB1_HOST PDL_OFF
622
623// Watch Counter
624#define PDL_INTERRUPT_ENABLE_WC0 PDL_OFF
625
626// Watchdog Timers
627#define PDL_INTERRUPT_ENABLE_HWWDG PDL_OFF
628#define PDL_INTERRUPT_ENABLE_SWWDG PDL_OFF
629
630/**
631 ******************************************************************************
632 ** User DSTC enable settings
633 **
634 ** Possible values are PDL_ON or PDL_OFF
635 ******************************************************************************/
636// ADC
637#define PDL_DSTC_ENABLE_ADC0_PRIO PDL_OFF
638#define PDL_DSTC_ENABLE_ADC0_SCAN PDL_OFF
639#define PDL_DSTC_ENABLE_ADC1_PRIO PDL_OFF
640#define PDL_DSTC_ENABLE_ADC1_SCAN PDL_OFF
641#define PDL_DSTC_ENABLE_ADC2_PRIO PDL_OFF
642#define PDL_DSTC_ENABLE_ADC2_SCAN PDL_OFF
643
644// BT
645#define PDL_DSTC_ENABLE_BT0_IRQ0 PDL_OFF
646#define PDL_DSTC_ENABLE_BT0_IRQ1 PDL_OFF
647#define PDL_DSTC_ENABLE_BT1_IRQ0 PDL_OFF
648#define PDL_DSTC_ENABLE_BT1_IRQ1 PDL_OFF
649#define PDL_DSTC_ENABLE_BT2_IRQ0 PDL_OFF
650#define PDL_DSTC_ENABLE_BT2_IRQ1 PDL_OFF
651#define PDL_DSTC_ENABLE_BT3_IRQ0 PDL_OFF
652#define PDL_DSTC_ENABLE_BT3_IRQ1 PDL_OFF
653#define PDL_DSTC_ENABLE_BT4_IRQ0 PDL_OFF
654#define PDL_DSTC_ENABLE_BT4_IRQ1 PDL_OFF
655#define PDL_DSTC_ENABLE_BT5_IRQ0 PDL_OFF
656#define PDL_DSTC_ENABLE_BT5_IRQ1 PDL_OFF
657#define PDL_DSTC_ENABLE_BT6_IRQ0 PDL_OFF
658#define PDL_DSTC_ENABLE_BT6_IRQ1 PDL_OFF
659#define PDL_DSTC_ENABLE_BT7_IRQ0 PDL_OFF
660#define PDL_DSTC_ENABLE_BT7_IRQ1 PDL_OFF
661#define PDL_DSTC_ENABLE_BT8_IRQ0 PDL_OFF
662#define PDL_DSTC_ENABLE_BT8_IRQ1 PDL_OFF
663#define PDL_DSTC_ENABLE_BT9_IRQ0 PDL_OFF
664#define PDL_DSTC_ENABLE_BT9_IRQ1 PDL_OFF
665#define PDL_DSTC_ENABLE_BT10_IRQ0 PDL_OFF
666#define PDL_DSTC_ENABLE_BT10_IRQ1 PDL_OFF
667#define PDL_DSTC_ENABLE_BT11_IRQ0 PDL_OFF
668#define PDL_DSTC_ENABLE_BT11_IRQ1 PDL_OFF
669#define PDL_DSTC_ENABLE_BT12_IRQ0 PDL_OFF
670#define PDL_DSTC_ENABLE_BT12_IRQ1 PDL_OFF
671#define PDL_DSTC_ENABLE_BT13_IRQ0 PDL_OFF
672#define PDL_DSTC_ENABLE_BT13_IRQ1 PDL_OFF
673#define PDL_DSTC_ENABLE_BT14_IRQ0 PDL_OFF
674#define PDL_DSTC_ENABLE_BT14_IRQ1 PDL_OFF
675#define PDL_DSTC_ENABLE_BT15_IRQ0 PDL_OFF
676#define PDL_DSTC_ENABLE_BT15_IRQ1 PDL_OFF
677
678// CAN-FD
679#define PDL_DSTC_ENABLE_CANFD0 PDL_OFF
680
681// EXINT
682#define PDL_DSTC_ENABLE_EXTINT0 PDL_OFF
683#define PDL_DSTC_ENABLE_EXTINT1 PDL_OFF
684#define PDL_DSTC_ENABLE_EXTINT2 PDL_OFF
685#define PDL_DSTC_ENABLE_EXTINT3 PDL_OFF
686#define PDL_DSTC_ENABLE_EXTINT4 PDL_OFF
687#define PDL_DSTC_ENABLE_EXTINT5 PDL_OFF
688#define PDL_DSTC_ENABLE_EXTINT6 PDL_OFF
689#define PDL_DSTC_ENABLE_EXTINT7 PDL_OFF
690#define PDL_DSTC_ENABLE_EXTINT8 PDL_OFF
691#define PDL_DSTC_ENABLE_EXTINT9 PDL_OFF
692#define PDL_DSTC_ENABLE_EXTINT10 PDL_OFF
693#define PDL_DSTC_ENABLE_EXTINT11 PDL_OFF
694#define PDL_DSTC_ENABLE_EXTINT12 PDL_OFF
695#define PDL_DSTC_ENABLE_EXTINT13 PDL_OFF
696#define PDL_DSTC_ENABLE_EXTINT14 PDL_OFF
697#define PDL_DSTC_ENABLE_EXTINT15 PDL_OFF
698#define PDL_DSTC_ENABLE_EXTINT16 PDL_OFF
699#define PDL_DSTC_ENABLE_EXTINT17 PDL_OFF
700#define PDL_DSTC_ENABLE_EXTINT18 PDL_OFF
701#define PDL_DSTC_ENABLE_EXTINT19 PDL_OFF
702#define PDL_DSTC_ENABLE_EXTINT20 PDL_OFF
703#define PDL_DSTC_ENABLE_EXTINT21 PDL_OFF
704#define PDL_DSTC_ENABLE_EXTINT22 PDL_OFF
705#define PDL_DSTC_ENABLE_EXTINT23 PDL_OFF
706#define PDL_DSTC_ENABLE_EXTINT24 PDL_OFF
707#define PDL_DSTC_ENABLE_EXTINT25 PDL_OFF
708#define PDL_DSTC_ENABLE_EXTINT26 PDL_OFF
709#define PDL_DSTC_ENABLE_EXTINT27 PDL_OFF
710#define PDL_DSTC_ENABLE_EXTINT28 PDL_OFF
711#define PDL_DSTC_ENABLE_EXTINT29 PDL_OFF
712#define PDL_DSTC_ENABLE_EXTINT30 PDL_OFF
713#define PDL_DSTC_ENABLE_EXTINT31 PDL_OFF
714
715// HSSPI
716#define PDL_DSTC_ENABLE_HSSPI0_TX PDL_OFF
717#define PDL_DSTC_ENABLE_HSSPI0_RX PDL_OFF
718
719// I2C Slave
720#define PDL_DSTC_ENABLE_I2CS0_RX PDL_OFF
721#define PDL_DSTC_ENABLE_I2CS0_TX PDL_OFF
722
723// I2S
724#define PDL_DSTC_ENABLE_I2S0_TX PDL_OFF
725#define PDL_DSTC_ENABLE_I2S0_RX PDL_OFF
726#define PDL_DSTC_ENABLE_I2S1_TX PDL_OFF
727#define PDL_DSTC_ENABLE_I2S1_RX PDL_OFF
728
729// MFS
730#define PDL_DSTC_ENABLE_MFS0_RX PDL_OFF
731#define PDL_DSTC_ENABLE_MFS0_TX PDL_OFF
732#define PDL_DSTC_ENABLE_MFS1_RX PDL_OFF
733#define PDL_DSTC_ENABLE_MFS1_TX PDL_OFF
734#define PDL_DSTC_ENABLE_MFS2_RX PDL_OFF
735#define PDL_DSTC_ENABLE_MFS2_TX PDL_OFF
736#define PDL_DSTC_ENABLE_MFS3_RX PDL_OFF
737#define PDL_DSTC_ENABLE_MFS3_TX PDL_OFF
738#define PDL_DSTC_ENABLE_MFS4_RX PDL_OFF
739#define PDL_DSTC_ENABLE_MFS4_TX PDL_OFF
740#define PDL_DSTC_ENABLE_MFS5_RX PDL_OFF
741#define PDL_DSTC_ENABLE_MFS5_TX PDL_OFF
742#define PDL_DSTC_ENABLE_MFS6_RX PDL_OFF
743#define PDL_DSTC_ENABLE_MFS6_TX PDL_OFF
744#define PDL_DSTC_ENABLE_MFS7_RX PDL_OFF
745#define PDL_DSTC_ENABLE_MFS7_TX PDL_OFF
746#define PDL_DSTC_ENABLE_MFS8_RX PDL_OFF
747#define PDL_DSTC_ENABLE_MFS8_TX PDL_OFF
748#define PDL_DSTC_ENABLE_MFS9_RX PDL_OFF
749#define PDL_DSTC_ENABLE_MFS9_TX PDL_OFF
750#define PDL_DSTC_ENABLE_MFS10_RX PDL_OFF
751#define PDL_DSTC_ENABLE_MFS10_TX PDL_OFF
752#define PDL_DSTC_ENABLE_MFS11_RX PDL_OFF
753#define PDL_DSTC_ENABLE_MFS11_TX PDL_OFF
754#define PDL_DSTC_ENABLE_MFS12_RX PDL_OFF
755#define PDL_DSTC_ENABLE_MFS12_TX PDL_OFF
756#define PDL_DSTC_ENABLE_MFS13_RX PDL_OFF
757#define PDL_DSTC_ENABLE_MFS13_TX PDL_OFF
758#define PDL_DSTC_ENABLE_MFS14_RX PDL_OFF
759#define PDL_DSTC_ENABLE_MFS14_TX PDL_OFF
760#define PDL_DSTC_ENABLE_MFS15_RX PDL_OFF
761#define PDL_DSTC_ENABLE_MFS15_TX PDL_OFF
762
763// MFT
764#define PDL_DSTC_ENABLE_MFT0_FRT0_PEAK PDL_OFF
765#define PDL_DSTC_ENABLE_MFT0_FRT0_ZERO PDL_OFF
766#define PDL_DSTC_ENABLE_MFT0_FRT1_PEAK PDL_OFF
767#define PDL_DSTC_ENABLE_MFT0_FRT1_ZERO PDL_OFF
768#define PDL_DSTC_ENABLE_MFT0_FRT2_PEAK PDL_OFF
769#define PDL_DSTC_ENABLE_MFT0_FRT2_ZERO PDL_OFF
770#define PDL_DSTC_ENABLE_MFT0_ICU0 PDL_OFF
771#define PDL_DSTC_ENABLE_MFT0_ICU1 PDL_OFF
772#define PDL_DSTC_ENABLE_MFT0_ICU2 PDL_OFF
773#define PDL_DSTC_ENABLE_MFT0_ICU3 PDL_OFF
774#define PDL_DSTC_ENABLE_MFT0_OCU0 PDL_OFF
775#define PDL_DSTC_ENABLE_MFT0_OCU1 PDL_OFF
776#define PDL_DSTC_ENABLE_MFT0_OCU2 PDL_OFF
777#define PDL_DSTC_ENABLE_MFT0_OCU3 PDL_OFF
778#define PDL_DSTC_ENABLE_MFT0_OCU4 PDL_OFF
779#define PDL_DSTC_ENABLE_MFT0_OCU5 PDL_OFF
780#define PDL_DSTC_ENABLE_MFT0_WFG10 PDL_OFF
781#define PDL_DSTC_ENABLE_MFT0_WFG32 PDL_OFF
782#define PDL_DSTC_ENABLE_MFT0_WFG54 PDL_OFF
783#define PDL_DSTC_ENABLE_MFT1_FRT0_PEAK PDL_OFF
784#define PDL_DSTC_ENABLE_MFT1_FRT0_ZERO PDL_OFF
785#define PDL_DSTC_ENABLE_MFT1_FRT1_PEAK PDL_OFF
786#define PDL_DSTC_ENABLE_MFT1_FRT1_ZERO PDL_OFF
787#define PDL_DSTC_ENABLE_MFT1_FRT2_PEAK PDL_OFF
788#define PDL_DSTC_ENABLE_MFT1_FRT2_ZERO PDL_OFF
789#define PDL_DSTC_ENABLE_MFT1_ICU0 PDL_OFF
790#define PDL_DSTC_ENABLE_MFT1_ICU1 PDL_OFF
791#define PDL_DSTC_ENABLE_MFT1_ICU2 PDL_OFF
792#define PDL_DSTC_ENABLE_MFT1_ICU3 PDL_OFF
793#define PDL_DSTC_ENABLE_MFT1_OCU0 PDL_OFF
794#define PDL_DSTC_ENABLE_MFT1_OCU1 PDL_OFF
795#define PDL_DSTC_ENABLE_MFT1_OCU2 PDL_OFF
796#define PDL_DSTC_ENABLE_MFT1_OCU3 PDL_OFF
797#define PDL_DSTC_ENABLE_MFT1_OCU4 PDL_OFF
798#define PDL_DSTC_ENABLE_MFT1_OCU5 PDL_OFF
799#define PDL_DSTC_ENABLE_MFT1_WFG10 PDL_OFF
800#define PDL_DSTC_ENABLE_MFT1_WFG32 PDL_OFF
801#define PDL_DSTC_ENABLE_MFT1_WFG54 PDL_OFF
802#define PDL_DSTC_ENABLE_MFT2_FRT0_PEAK PDL_OFF
803#define PDL_DSTC_ENABLE_MFT2_FRT0_ZERO PDL_OFF
804#define PDL_DSTC_ENABLE_MFT2_FRT1_PEAK PDL_OFF
805#define PDL_DSTC_ENABLE_MFT2_FRT1_ZERO PDL_OFF
806#define PDL_DSTC_ENABLE_MFT2_FRT2_PEAK PDL_OFF
807#define PDL_DSTC_ENABLE_MFT2_FRT2_ZERO PDL_OFF
808#define PDL_DSTC_ENABLE_MFT2_ICU0 PDL_OFF
809#define PDL_DSTC_ENABLE_MFT2_ICU1 PDL_OFF
810#define PDL_DSTC_ENABLE_MFT2_ICU2 PDL_OFF
811#define PDL_DSTC_ENABLE_MFT2_ICU3 PDL_OFF
812#define PDL_DSTC_ENABLE_MFT2_OCU0 PDL_OFF
813#define PDL_DSTC_ENABLE_MFT2_OCU1 PDL_OFF
814#define PDL_DSTC_ENABLE_MFT2_OCU2 PDL_OFF
815#define PDL_DSTC_ENABLE_MFT2_OCU3 PDL_OFF
816#define PDL_DSTC_ENABLE_MFT2_OCU4 PDL_OFF
817#define PDL_DSTC_ENABLE_MFT2_OCU5 PDL_OFF
818#define PDL_DSTC_ENABLE_MFT2_WFG10 PDL_OFF
819#define PDL_DSTC_ENABLE_MFT2_WFG32 PDL_OFF
820#define PDL_DSTC_ENABLE_MFT2_WFG54 PDL_OFF
821
822// Programmable CRC
823#define PDL_DSTC_ENABLE_PCRC PDL_OFF
824
825// PPG
826#define PDL_DSTC_ENABLE_PPG0 PDL_OFF
827#define PDL_DSTC_ENABLE_PPG2 PDL_OFF
828#define PDL_DSTC_ENABLE_PPG4 PDL_OFF
829#define PDL_DSTC_ENABLE_PPG8 PDL_OFF
830#define PDL_DSTC_ENABLE_PPG10 PDL_OFF
831#define PDL_DSTC_ENABLE_PPG12 PDL_OFF
832#define PDL_DSTC_ENABLE_PPG16 PDL_OFF
833#define PDL_DSTC_ENABLE_PPG18 PDL_OFF
834#define PDL_DSTC_ENABLE_PPG20 PDL_OFF
835
836// QPRC
837#define PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION PDL_OFF
838#define PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE PDL_OFF
839#define PDL_DSTC_ENABLE_QPRC0_PC_MATCH PDL_OFF
840#define PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH PDL_OFF
841#define PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH PDL_OFF
842#define PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z PDL_OFF
843#define PDL_DSTC_ENABLE_QPRC1_COUNT_INVERSION PDL_OFF
844#define PDL_DSTC_ENABLE_QPRC1_OUT_OF_RANGE PDL_OFF
845#define PDL_DSTC_ENABLE_QPRC1_PC_MATCH PDL_OFF
846#define PDL_DSTC_ENABLE_QPRC1_PC_MATCH_RC_MATCH PDL_OFF
847#define PDL_DSTC_ENABLE_QPRC1_PC_RC_MATCH PDL_OFF
848#define PDL_DSTC_ENABLE_QPRC1_UFL_OFL_Z PDL_OFF
849#define PDL_DSTC_ENABLE_QPRC2_COUNT_INVERSION PDL_OFF
850#define PDL_DSTC_ENABLE_QPRC2_OUT_OF_RANGE PDL_OFF
851#define PDL_DSTC_ENABLE_QPRC2_PC_MATCH PDL_OFF
852#define PDL_DSTC_ENABLE_QPRC2_PC_MATCH_RC_MATCH PDL_OFF
853#define PDL_DSTC_ENABLE_QPRC2_PC_RC_MATCH PDL_OFF
854#define PDL_DSTC_ENABLE_QPRC2_UFL_OFL_Z PDL_OFF
855#define PDL_DSTC_ENABLE_QPRC3_COUNT_INVERSION PDL_OFF
856#define PDL_DSTC_ENABLE_QPRC3_OUT_OF_RANGE PDL_OFF
857#define PDL_DSTC_ENABLE_QPRC3_PC_MATCH PDL_OFF
858#define PDL_DSTC_ENABLE_QPRC3_PC_MATCH_RC_MATCH PDL_OFF
859#define PDL_DSTC_ENABLE_QPRC3_PC_RC_MATCH PDL_OFF
860#define PDL_DSTC_ENABLE_QPRC3_UFL_OFL_Z PDL_OFF
861
862// USB
863#define PDL_DSTC_ENABLE_USB0_EP1 PDL_OFF
864#define PDL_DSTC_ENABLE_USB0_EP2 PDL_OFF
865#define PDL_DSTC_ENABLE_USB0_EP3 PDL_OFF
866#define PDL_DSTC_ENABLE_USB0_EP4 PDL_OFF
867#define PDL_DSTC_ENABLE_USB0_EP5 PDL_OFF
868#define PDL_DSTC_ENABLE_USB1_EP1 PDL_OFF
869#define PDL_DSTC_ENABLE_USB1_EP2 PDL_OFF
870#define PDL_DSTC_ENABLE_USB1_EP3 PDL_OFF
871#define PDL_DSTC_ENABLE_USB1_EP4 PDL_OFF
872#define PDL_DSTC_ENABLE_USB1_EP5 PDL_OFF
873
874// WC
875#define PDL_DSTC_ENABLE_WC PDL_OFF
876
877/**
878 ******************************************************************************
879 ** User Interrupt level settings
880 **
881 ** Possible values are 0 (high priority) to 15 (low priority)
882 ******************************************************************************/
883#if (PDL_MCU_CORE == PDL_FM4_CORE) // FM4
884// Analog Digital Converters
885#define PDL_IRQ_LEVEL_ADC0 15u // slow
886#define PDL_IRQ_LEVEL_ADC1 2u // fast adc must be higher than BT*
887#define PDL_IRQ_LEVEL_ADC2 15u
888
889// Base Timers
890#define PDL_IRQ_LEVEL_BT0 4u
891#define PDL_IRQ_LEVEL_BT1 4u
892#define PDL_IRQ_LEVEL_BT2 3u // adcfast timer has more priority
893#define PDL_IRQ_LEVEL_BT3 3u
894#define PDL_IRQ_LEVEL_BT4 15u
895#define PDL_IRQ_LEVEL_BT5 15u
896#define PDL_IRQ_LEVEL_BT6 15u
897#define PDL_IRQ_LEVEL_BT7 15u
898#define PDL_IRQ_LEVEL_BT8 15u
899#define PDL_IRQ_LEVEL_BT9 15u
900#define PDL_IRQ_LEVEL_BT10 15u
901#define PDL_IRQ_LEVEL_BT11 15u
902#define PDL_IRQ_LEVEL_BT12_13_14_15 15u
903
904// CAN
905#define PDL_IRQ_LEVEL_CAN0 15u
906#define PDL_IRQ_LEVEL_CAN1_CANFD0 15u // 6u
907
908// Clock Stabilization Irq
909#define PDL_IRQ_LEVEL_CLK 15u
910
911// Clock Supervisor
912#define PDL_IRQ_LEVEL_CSV 15u
913
914// DMA
915#define PDL_IRQ_LEVEL_DMA0 15u
916#define PDL_IRQ_LEVEL_DMA1 15u
917#define PDL_IRQ_LEVEL_DMA2 15u
918#define PDL_IRQ_LEVEL_DMA3 15u
919#define PDL_IRQ_LEVEL_DMA4 15u
920#define PDL_IRQ_LEVEL_DMA5 15u
921#define PDL_IRQ_LEVEL_DMA6 15u
922#define PDL_IRQ_LEVEL_DMA7 15u
923
924// DSTC
925#define PDL_IRQ_LEVEL_DSTC 15u
926
927// Dual Timer(s)
928#define PDL_IRQ_LEVEL_DT0 15u
929
930// Ethernet
931// Please set IRQ level in emac_user.h
932
933// External Bus Interface
934#define PDL_IRQ_LEVEL_EXTIF 15u
935
936// External Interrupts + NMI
937#define PDL_IRQ_LEVEL_EXINT0 2u // the same as fast ADC
938#define PDL_IRQ_LEVEL_EXINT1 2u
939#define PDL_IRQ_LEVEL_EXINT2 2u
940#define PDL_IRQ_LEVEL_EXINT3 2u
941#define PDL_IRQ_LEVEL_EXINT4 2u
942#define PDL_IRQ_LEVEL_EXINT5 2u
943#define PDL_IRQ_LEVEL_EXINT6 2u
944#define PDL_IRQ_LEVEL_EXINT7 2u
945#define PDL_IRQ_LEVEL_EXINT8 2u
946#define PDL_IRQ_LEVEL_EXINT9 2u
947#define PDL_IRQ_LEVEL_EXINT10 2u
948#define PDL_IRQ_LEVEL_EXINT11 2u
949#define PDL_IRQ_LEVEL_EXINT12 2u
950#define PDL_IRQ_LEVEL_EXINT13 2u
951#define PDL_IRQ_LEVEL_EXINT14 2u
952#define PDL_IRQ_LEVEL_EXINT15 2u
953#define PDL_IRQ_LEVEL_EXINT16_17_18_19 2u
954#define PDL_IRQ_LEVEL_EXINT20_21_22_23 2u
955#define PDL_IRQ_LEVEL_EXINT24_25_26_27 2u
956#define PDL_IRQ_LEVEL_EXINT28_29_30_31 2u
957
958// Hyper Bus Interface
959#define PDL_IRQ_LEVEL_HBIF 15u
960
961// High Speed Quad SPI
962#define PDL_IRQ_LEVEL_HSSPI0 15u
963
964// I2S and Programmable CRC
965#define PDL_IRQ_LEVEL_I2S_PCRC 15u
966
967// IC Card
968#define PDL_IRQ_LEVEL_ICC0_1 15u
969
970// Low Voltage Detection Interrupt
971#define PDL_IRQ_LEVEL_LVD 15u
972
973// Multi Function Serial Interfaces
974#define PDL_IRQ_LEVEL_MFS0_TX 15u
975#define PDL_IRQ_LEVEL_MFS0_RX 15u
976#define PDL_IRQ_LEVEL_MFS1_TX 15u
977#define PDL_IRQ_LEVEL_MFS1_RX 15u
978#define PDL_IRQ_LEVEL_MFS2_TX 15u
979#define PDL_IRQ_LEVEL_MFS2_RX 15u
980#define PDL_IRQ_LEVEL_MFS3_TX 15u
981#define PDL_IRQ_LEVEL_MFS3_RX 15u
982#define PDL_IRQ_LEVEL_MFS4_TX 15u
983#define PDL_IRQ_LEVEL_MFS4_RX 15u
984#define PDL_IRQ_LEVEL_MFS5_TX 15u
985#define PDL_IRQ_LEVEL_MFS5_RX 15u
986#define PDL_IRQ_LEVEL_MFS6_TX 15u
987#define PDL_IRQ_LEVEL_MFS6_RX 15u
988#define PDL_IRQ_LEVEL_MFS7_TX 15u
989#define PDL_IRQ_LEVEL_MFS7_RX 15u
990#define PDL_IRQ_LEVEL_MFS8_TX 15u
991#define PDL_IRQ_LEVEL_MFS8_RX 15u
992#define PDL_IRQ_LEVEL_MFS9_TX 15u
993#define PDL_IRQ_LEVEL_MFS9_RX 15u
994#define PDL_IRQ_LEVEL_MFS10_TX 15u
995#define PDL_IRQ_LEVEL_MFS10_RX 15u
996#define PDL_IRQ_LEVEL_MFS11_TX 15u
997#define PDL_IRQ_LEVEL_MFS11_RX 15u
998#define PDL_IRQ_LEVEL_MFS12_TX 15u
999#define PDL_IRQ_LEVEL_MFS12_RX 15u
1000#define PDL_IRQ_LEVEL_MFS13_TX 15u
1001#define PDL_IRQ_LEVEL_MFS13_RX 15u
1002#define PDL_IRQ_LEVEL_MFS14_TX 15u
1003#define PDL_IRQ_LEVEL_MFS14_RX 15u
1004#define PDL_IRQ_LEVEL_MFS15_TX 15u
1005#define PDL_IRQ_LEVEL_MFS15_RX 15u
1006
1007// Multi Function Timer Interrupts
1008#define PDL_IRQ_LEVEL_MFT0_FRT 15u
1009#define PDL_IRQ_LEVEL_MFT0_OCU 15u
1010#define PDL_IRQ_LEVEL_MFT0_WFG 15u
1011#define PDL_IRQ_LEVEL_MFT0_ICU 15u
1012
1013#define PDL_IRQ_LEVEL_MFT1_FRT 15u
1014#define PDL_IRQ_LEVEL_MFT1_OCU 15u
1015#define PDL_IRQ_LEVEL_MFT1_WFG 15u
1016#define PDL_IRQ_LEVEL_MFT1_ICU 15u
1017
1018#define PDL_IRQ_LEVEL_MFT2_FRT 15u
1019#define PDL_IRQ_LEVEL_MFT2_OCU 15u
1020#define PDL_IRQ_LEVEL_MFT2_WFG 15u
1021#define PDL_IRQ_LEVEL_MFT2_ICU 15u
1022
1023// NMI
1024#define PDL_IRQ_LEVEL_NMI 15u
1025
1026// PPG Interrupts
1027#define PDL_IRQ_LEVEL_PPG00_02_04 15u
1028#define PDL_IRQ_LEVEL_PPG08_10_12 15u
1029#define PDL_IRQ_LEVEL_PPG16_18_20 15u
1030
1031// Quad Decoder and Revolution Counter
1032#define PDL_IRQ_LEVEL_QPRC0 15u
1033#define PDL_IRQ_LEVEL_QPRC1 15u
1034#define PDL_IRQ_LEVEL_QPRC2 15u
1035#define PDL_IRQ_LEVEL_QPRC3 15u
1036
1037// Real Time Clock
1038#define PDL_IRQ_LEVEL_RTC0 15u
1039
1040// SD Host
1041#define PDL_IRQ_LEVEL_SD 15u
1042
1043// USB
1044#define PDL_IRQ_LEVEL_USB0 6u
1045#define PDL_IRQ_LEVEL_USB1 6u
1046
1047// Watch Counter
1048#define PDL_IRQ_LEVEL_WC0 15u
1049
1050// Watchdog Timers
1051#define PDL_IRQ_LEVEL_HWWDG 15u
1052#define PDL_IRQ_LEVEL_SWWDG 15u
1053
1054#else
1055#error MCU core not found!
1056#endif
1057/**
1058 ******************************************************************************
1059 ** PDL resource activiation check
1060 **
1061 ** \note It does not check, if a device has actually all instances available!
1062 **
1063 ******************************************************************************/
1064// Activate code in adc.c if one or more are set to PDL_ON
1065#if (PDL_PERIPHERAL_ENABLE_ADC0 == PDL_ON) || \
1066 (PDL_PERIPHERAL_ENABLE_ADC1 == PDL_ON) || \
1067 (PDL_PERIPHERAL_ENABLE_ADC2 == PDL_ON)
1068 #define PDL_PERIPHERAL_ADC_ACTIVE
1069#endif
1070
1071// Activate code in aes.c if set to PDL_ON
1072#if (PDL_PERIPHERAL_ENABLE_AES == PDL_ON)
1073 #define PDL_PERIPHERAL_AES_ACTIVE
1074#endif
1075
1076// Activate code in bt.c if one or more are set to PDL_ON
1077#if (PDL_PERIPHERAL_ENABLE_BT0 == PDL_ON) || \
1078 (PDL_PERIPHERAL_ENABLE_BT1 == PDL_ON) || \
1079 (PDL_PERIPHERAL_ENABLE_BT2 == PDL_ON) || \
1080 (PDL_PERIPHERAL_ENABLE_BT3 == PDL_ON) || \
1081 (PDL_PERIPHERAL_ENABLE_BT4 == PDL_ON) || \
1082 (PDL_PERIPHERAL_ENABLE_BT5 == PDL_ON) || \
1083 (PDL_PERIPHERAL_ENABLE_BT6 == PDL_ON) || \
1084 (PDL_PERIPHERAL_ENABLE_BT7 == PDL_ON) || \
1085 (PDL_PERIPHERAL_ENABLE_BT8 == PDL_ON) || \
1086 (PDL_PERIPHERAL_ENABLE_BT9 == PDL_ON) || \
1087 (PDL_PERIPHERAL_ENABLE_BT10 == PDL_ON) || \
1088 (PDL_PERIPHERAL_ENABLE_BT11 == PDL_ON) || \
1089 (PDL_PERIPHERAL_ENABLE_BT12 == PDL_ON) || \
1090 (PDL_PERIPHERAL_ENABLE_BT13 == PDL_ON) || \
1091 (PDL_PERIPHERAL_ENABLE_BT14 == PDL_ON) || \
1092 (PDL_PERIPHERAL_ENABLE_BT15 == PDL_ON)
1093 #define PDL_PERIPHERAL_BT_ACTIVE
1094#endif
1095
1096// Activate code in can.c if set to PDL_ON
1097#if (PDL_PERIPHERAL_ENABLE_CAN0 == PDL_ON) || \
1098 (PDL_PERIPHERAL_ENABLE_CAN1 == PDL_ON)
1099 #define PDL_PERIPHERAL_CAN_ACTIVE
1100#endif
1101
1102// Activate code in canfd.c if set to PDL_ON
1103#if (PDL_PERIPHERAL_ENABLE_CANFD0 == PDL_ON) || \
1104 (PDL_PERIPHERAL_ENABLE_CANFD1 == PDL_ON)
1105 #define PDL_PERIPHERAL_CANFD_ACTIVE
1106#endif
1107
1108// Activate code in crc.c if set to PDL_ON
1109#if (PDL_PERIPHERAL_ENABLE_CRC0 == PDL_ON)
1110 #define PDL_PERIPHERAL_CRC_ACTIVE
1111#endif
1112
1113// Activate code in clk.c if set to PDL_ON or WC enabled
1114#if (PDL_PERIPHERAL_ENABLE_CLK == PDL_ON)
1115 #define PDL_PERIPHERAL_CLK_ACTIVE
1116#endif
1117
1118// Activate code in crtrim.c if set to PDL_ON
1119#if (PDL_PERIPHERAL_ENABLE_CR == PDL_ON)
1120 #define PDL_PERIPHERAL_CR_ACTIVE
1121#endif
1122
1123// Activate code in csv.c if set to PDL_ON
1124#if (PDL_PERIPHERAL_ENABLE_CSV == PDL_ON)
1125 #define PDL_PERIPHERAL_CSV_ACTIVE
1126#endif
1127
1128// Activate code in dac.c if one or more are set to PDL_ON
1129#if (PDL_PERIPHERAL_ENABLE_DAC0 == PDL_ON)
1130 #define PDL_PERIPHERAL_DAC_ACTIVE
1131#endif
1132
1133// Activate code for dma.c
1134#if (PDL_PERIPHERAL_ENABLE_DMA0 == PDL_ON) || \
1135 (PDL_PERIPHERAL_ENABLE_DMA1 == PDL_ON) || \
1136 (PDL_PERIPHERAL_ENABLE_DMA2 == PDL_ON) || \
1137 (PDL_PERIPHERAL_ENABLE_DMA3 == PDL_ON) || \
1138 (PDL_PERIPHERAL_ENABLE_DMA4 == PDL_ON) || \
1139 (PDL_PERIPHERAL_ENABLE_DMA5 == PDL_ON) || \
1140 (PDL_PERIPHERAL_ENABLE_DMA6 == PDL_ON) || \
1141 (PDL_PERIPHERAL_ENABLE_DMA7 == PDL_ON)
1142 #define PDL_PERIPHERAL_DMA_ACTIVE
1143#endif
1144
1145// Activate code in dstc.c if one or more are set to PDL_ON
1146#if (PDL_PERIPHERAL_ENABLE_DSTC == PDL_ON)
1147 #define PDL_PERIPHERAL_DSTC_ACTIVE
1148#endif
1149
1150// Activate code in dt.c if one or more are set to PDL_ON
1151#if (PDL_PERIPHERAL_ENABLE_DT0 == PDL_ON)
1152 #define PDL_PERIPHERAL_DT_ACTIVE
1153#endif
1154
1155// Activate code in exint.c if one or more are set to PDL_ON
1156#if (PDL_PERIPHERAL_ENABLE_EXINT0 == PDL_ON) || \
1157 (PDL_PERIPHERAL_ENABLE_EXINT1 == PDL_ON) || \
1158 (PDL_PERIPHERAL_ENABLE_EXINT2 == PDL_ON) || \
1159 (PDL_PERIPHERAL_ENABLE_EXINT3 == PDL_ON) || \
1160 (PDL_PERIPHERAL_ENABLE_EXINT4 == PDL_ON) || \
1161 (PDL_PERIPHERAL_ENABLE_EXINT5 == PDL_ON) || \
1162 (PDL_PERIPHERAL_ENABLE_EXINT6 == PDL_ON) || \
1163 (PDL_PERIPHERAL_ENABLE_EXINT7 == PDL_ON) || \
1164 (PDL_PERIPHERAL_ENABLE_EXINT8 == PDL_ON) || \
1165 (PDL_PERIPHERAL_ENABLE_EXINT9 == PDL_ON) || \
1166 (PDL_PERIPHERAL_ENABLE_EXINT10 == PDL_ON) || \
1167 (PDL_PERIPHERAL_ENABLE_EXINT11 == PDL_ON) || \
1168 (PDL_PERIPHERAL_ENABLE_EXINT12 == PDL_ON) || \
1169 (PDL_PERIPHERAL_ENABLE_EXINT13 == PDL_ON) || \
1170 (PDL_PERIPHERAL_ENABLE_EXINT14 == PDL_ON) || \
1171 (PDL_PERIPHERAL_ENABLE_EXINT15 == PDL_ON) || \
1172 (PDL_PERIPHERAL_ENABLE_EXINT16 == PDL_ON) || \
1173 (PDL_PERIPHERAL_ENABLE_EXINT17 == PDL_ON) || \
1174 (PDL_PERIPHERAL_ENABLE_EXINT18 == PDL_ON) || \
1175 (PDL_PERIPHERAL_ENABLE_EXINT19 == PDL_ON) || \
1176 (PDL_PERIPHERAL_ENABLE_EXINT20 == PDL_ON) || \
1177 (PDL_PERIPHERAL_ENABLE_EXINT21 == PDL_ON) || \
1178 (PDL_PERIPHERAL_ENABLE_EXINT22 == PDL_ON) || \
1179 (PDL_PERIPHERAL_ENABLE_EXINT23 == PDL_ON) || \
1180 (PDL_PERIPHERAL_ENABLE_EXINT24 == PDL_ON) || \
1181 (PDL_PERIPHERAL_ENABLE_EXINT25 == PDL_ON) || \
1182 (PDL_PERIPHERAL_ENABLE_EXINT26 == PDL_ON) || \
1183 (PDL_PERIPHERAL_ENABLE_EXINT27 == PDL_ON) || \
1184 (PDL_PERIPHERAL_ENABLE_EXINT28 == PDL_ON) || \
1185 (PDL_PERIPHERAL_ENABLE_EXINT29 == PDL_ON) || \
1186 (PDL_PERIPHERAL_ENABLE_EXINT30 == PDL_ON) || \
1187 (PDL_PERIPHERAL_ENABLE_EXINT31 == PDL_ON)
1188 #define PDL_PERIPHERAL_EXINT_ACTIVE
1189#endif
1190
1191// Activate code in extif.c if set to PDL_ON
1192#if (PDL_PERIPHERAL_ENABLE_EXTIF == PDL_ON)
1193 #define PDL_PERIPHERAL_EXTIF_ACTIVE
1194#endif
1195
1196// Activate code in dualflash.c if set to PDL_ON
1197#if (PDL_PERIPHERAL_ENABLE_DUAL_FLASH == PDL_ON)
1198 #define PDL_PERIPHERAL_DUAL_FLASH_ACTIVE
1199#endif
1200
1201// Activate code in mainflash.c if set to PDL_ON
1202#if (PDL_PERIPHERAL_ENABLE_MAIN_FLASH == PDL_ON)
1203 #define PDL_PERIPHERAL_MAIN_FLASH_ACTIVE
1204#endif
1205
1206// Activate code in workflash.c if set to PDL_ON
1207#if (PDL_PERIPHERAL_ENABLE_WORK_FLASH == PDL_ON)
1208 #define PDL_PERIPHERAL_WORK_FLASH_ACTIVE
1209#endif
1210
1211// Activate code in gpio.h if set to PDL_ON
1212#if (PDL_PERIPHERAL_ENABLE_GPIO == PDL_ON)
1213 #define PDL_PERIPHERAL_GPIO_ACTIVE
1214#endif
1215
1216// Activate code in hbif.h if set to PDL_ON
1217#if (PDL_PERIPHERAL_ENABLE_HBIF == PDL_ON)
1218 #define PDL_PERIPHERAL_HBIF_ACTIVE
1219#endif
1220
1221// Activate code in hsspi.h if set to PDL_ON
1222#if (PDL_PERIPHERAL_ENABLE_HSSPI0 == PDL_ON)
1223 #define PDL_PERIPHERAL_HSSPI_ACTIVE
1224#endif
1225
1226// Activate code in i2cs.h if set to PDL_ON
1227#if (PDL_PERIPHERAL_ENABLE_I2CS0 == PDL_ON)
1228 #define PDL_PERIPHERAL_I2CS_ACTIVE
1229#endif
1230
1231// Activate code in icc.h if set to PDL_ON
1232#if (PDL_PERIPHERAL_ENABLE_ICC0 == PDL_ON) || \
1233 (PDL_PERIPHERAL_ENABLE_ICC1 == PDL_ON)
1234 #define PDL_PERIPHERAL_ICC_ACTIVE
1235#endif
1236
1237// Activate code in i2s.h if set to PDL_ON
1238#if (PDL_PERIPHERAL_ENABLE_I2S0 == PDL_ON) || \
1239 (PDL_PERIPHERAL_ENABLE_I2S1 == PDL_ON)
1240 #define PDL_PERIPHERAL_I2S_ACTIVE
1241#endif
1242
1243// Activate code in i2sl.h if set to PDL_ON
1244#if (PDL_PERIPHERAL_ENABLE_I2SL0 == PDL_ON) || \
1245 (PDL_PERIPHERAL_ENABLE_I2SL1 == PDL_ON)
1246 #define PDL_PERIPHERAL_I2SL_ACTIVE
1247#endif
1248
1249// Activate code in lcd.c if set to PDL_ON
1250#if (PDL_PERIPHERAL_ENABLE_LCD == PDL_ON)
1251 #define PDL_PERIPHERAL_LCD_ACTIVE
1252#endif
1253
1254// Activate code in lpm.c if set to PDL_ON
1255#if (PDL_PERIPHERAL_ENABLE_LPM == PDL_ON)
1256 #define PDL_PERIPHERAL_LPM_ACTIVE
1257#endif
1258
1259// Activate code in lvd.c if set to PDL_ON
1260#if (PDL_PERIPHERAL_ENABLE_LVD == PDL_ON)
1261 #define PDL_PERIPHERAL_LVD_ACTIVE
1262#endif
1263
1264// Activate code in mfs.c if one or more are set to PDL_ON
1265#if (PDL_PERIPHERAL_ENABLE_MFS0 == PDL_ON) || \
1266 (PDL_PERIPHERAL_ENABLE_MFS1 == PDL_ON) || \
1267 (PDL_PERIPHERAL_ENABLE_MFS2 == PDL_ON) || \
1268 (PDL_PERIPHERAL_ENABLE_MFS3 == PDL_ON) || \
1269 (PDL_PERIPHERAL_ENABLE_MFS4 == PDL_ON) || \
1270 (PDL_PERIPHERAL_ENABLE_MFS5 == PDL_ON) || \
1271 (PDL_PERIPHERAL_ENABLE_MFS6 == PDL_ON) || \
1272 (PDL_PERIPHERAL_ENABLE_MFS7 == PDL_ON) || \
1273 (PDL_PERIPHERAL_ENABLE_MFS8 == PDL_ON) || \
1274 (PDL_PERIPHERAL_ENABLE_MFS9 == PDL_ON) || \
1275 (PDL_PERIPHERAL_ENABLE_MFS10 == PDL_ON) || \
1276 (PDL_PERIPHERAL_ENABLE_MFS11 == PDL_ON) || \
1277 (PDL_PERIPHERAL_ENABLE_MFS12 == PDL_ON) || \
1278 (PDL_PERIPHERAL_ENABLE_MFS13 == PDL_ON) || \
1279 (PDL_PERIPHERAL_ENABLE_MFS14 == PDL_ON) || \
1280 (PDL_PERIPHERAL_ENABLE_MFS15 == PDL_ON)
1281 #define PDL_PERIPHERAL_MFS_ACTIVE
1282#endif
1283
1284// Activate code in mft_frt.c if one or more are set to PDL_ON
1285#if (PDL_PERIPHERAL_ENABLE_MFT0_FRT == PDL_ON) || \
1286 (PDL_PERIPHERAL_ENABLE_MFT1_FRT == PDL_ON) || \
1287 (PDL_PERIPHERAL_ENABLE_MFT2_FRT == PDL_ON)
1288 #define PDL_PERIPHERAL_MFT_FRT_ACTIVE
1289#endif
1290
1291// Activate code in mft_ocu.c if one or more are set to PDL_ON
1292#if (PDL_PERIPHERAL_ENABLE_MFT0_OCU == PDL_ON) || \
1293 (PDL_PERIPHERAL_ENABLE_MFT1_OCU == PDL_ON) || \
1294 (PDL_PERIPHERAL_ENABLE_MFT2_OCU == PDL_ON)
1295 #define PDL_PERIPHERAL_MFT_OCU_ACTIVE
1296#endif
1297
1298// Activate code in mft_wfg.c if one or more are set to PDL_ON
1299#if (PDL_PERIPHERAL_ENABLE_MFT0_WFG == PDL_ON) || \
1300 (PDL_PERIPHERAL_ENABLE_MFT1_WFG == PDL_ON) || \
1301 (PDL_PERIPHERAL_ENABLE_MFT2_WFG == PDL_ON)
1302 #define PDL_PERIPHERAL_MFT_WFG_ACTIVE
1303#endif
1304
1305// Activate code in mft_icu.c if one or more are set to PDL_ON
1306#if (PDL_PERIPHERAL_ENABLE_MFT0_ICU == PDL_ON) || \
1307 (PDL_PERIPHERAL_ENABLE_MFT1_ICU == PDL_ON) || \
1308 (PDL_PERIPHERAL_ENABLE_MFT2_ICU == PDL_ON)
1309 #define PDL_PERIPHERAL_MFT_ICU_ACTIVE
1310#endif
1311
1312// Activate code in mft_adcmp.c if one or more are set to PDL_ON
1313#if (PDL_PERIPHERAL_ENABLE_MFT0_ADCMP == PDL_ON) || \
1314 (PDL_PERIPHERAL_ENABLE_MFT1_ADCMP == PDL_ON) || \
1315 (PDL_PERIPHERAL_ENABLE_MFT2_ADCMP == PDL_ON)
1316 #define PDL_PERIPHERAL_MFT_ADCMP_ACTIVE
1317#endif
1318
1319// Activate NMI code in exint.c if one or more are set to PDL_ON
1320#if (PDL_PERIPHERAL_ENABLE_NMI == PDL_ON)
1321 #define PDL_PERIPHERAL_NMI_ACTIVE
1322#endif
1323
1324// Activate code in pcrc.c if one or more are set to PDL_ON
1325#if (PDL_PERIPHERAL_ENABLE_PCRC == PDL_ON)
1326 #define PDL_PERIPHERAL_PCRC_ACTIVE
1327#endif
1328
1329// Activate code in ppg.c if one or more are set to PDL_ON
1330#if (PDL_PERIPHERAL_ENABLE_PPG == PDL_ON)
1331 #define PDL_PERIPHERAL_PPG_ACTIVE
1332#endif
1333
1334// Activate code in qprc.c if set to PDL_ON
1335#if (PDL_PERIPHERAL_ENABLE_QPRC0 == PDL_ON) || \
1336 (PDL_PERIPHERAL_ENABLE_QPRC1 == PDL_ON) || \
1337 (PDL_PERIPHERAL_ENABLE_QPRC2 == PDL_ON)
1338 #define PDL_PERIPHERAL_QPRC_ACTIVE
1339#endif
1340
1341// Activate code in rc.c if set to PDL_ON
1342#if (PDL_PERIPHERAL_ENABLE_RC0 == PDL_ON) || \
1343 (PDL_PERIPHERAL_ENABLE_RC1 == PDL_ON)
1344 #define PDL_PERIPHERAL_RC_ACTIVE
1345#endif
1346
1347// Reset Cause
1348#if (PDL_PERIPHERAL_ENABLE_RESET == PDL_ON)
1349 #define PDL_PERIPHERAL_RESET_ACTIVE
1350#endif
1351
1352// Real Time Clock
1353#if (PDL_PERIPHERAL_ENABLE_RTC0 == PDL_ON)
1354 #define PDL_PERIPHERAL_RTC_ACTIVE
1355#endif
1356
1357// SD
1358#if (PDL_PERIPHERAL_ENABLE_SD0 == PDL_ON)
1359 #define PDL_PERIPHERAL_SD_ACTIVE
1360#endif
1361
1362// Unique ID
1363#if (PDL_PERIPHERAL_ENABLE_UID == PDL_ON)
1364 #define PDL_PERIPHERAL_UID_ACTIVE
1365#endif
1366
1367// Activate code in vbat.c if one or more are set to PDL_ON
1368#if (PDL_PERIPHERAL_ENABLE_VBAT == PDL_ON)
1369 #define PDL_PERIPHERAL_VBAT_ACTIVE
1370#endif
1371
1372// Activate code in wc.c if one or more are set to PDL_ON
1373#if (PDL_PERIPHERAL_ENABLE_WC0 == PDL_ON)
1374 #define PDL_PERIPHERAL_WC_ACTIVE
1375#endif
1376
1377// Activate code in wdg.c is set to PDL_ON
1378#if (PDL_PERIPHERAL_ENABLE_HWWDG == PDL_ON) || \
1379 (PDL_PERIPHERAL_ENABLE_SWWDG == PDL_ON)
1380 #define PDL_PERIPHERAL_WDG_ACTIVE
1381#endif
1382
1383/**
1384 ******************************************************************************
1385 ** \brief PDL utility enable setting
1386 ******************************************************************************/
1387// Printf/Scanf via UART function
1388#define PDL_UTILITY_ENABLE_UART_PRINTF PDL_OFF
1389#define PDL_UTILITY_ENABLE_UART_SCANF PDL_OFF
1390
1391// AT24CXX(EEPROM) driver
1392#define PDL_UTILITY_ENABLE_I2C_POLLING_AT24CXX PDL_OFF
1393#define PDL_UTILITY_ENABLE_I2C_IRQ_AT24CXX PDL_OFF
1394
1395// S25FL164K(SPI Flash) QSPI access driver with or without using interrupt
1396#define PDL_UTILITY_ENABLE_QSPI_POLLING_S25FL164K PDL_OFF
1397#define PDL_UTILITY_ENABLE_QSPI_IRQ_S25FL164K PDL_OFF
1398
1399// S26KL512S (Hyper Bus Flash) driver
1400#define PDL_UTILITY_ENABLE_HBIF_S26KL512S PDL_OFF
1401
1402// WM8731(I2S Codec) driver
1403#define PDL_UTILITY_ENABLE_I2S_CODEC_WM8731 PDL_OFF
1404
1405// SV6P1615(External Bus SRAM) driver
1406#define PDL_UTILITY_ENABLE_EXTIF_SV6P1615 PDL_OFF
1407
1408// IS42S16800(SDRAM) driver
1409#define PDL_UTILITY_ENABLE_EXTIF_IS42S16800 PDL_OFF
1410
1411// HY57V281620(SDRAM) driver
1412#define PDL_UTILITY_ENABLE_EXTIF_HY57V281620 PDL_OFF
1413
1414// K9F5608U0D (Nand Flash) driver
1415#define PDL_UTILITY_ENABLE_EXTIF_K9F5608U0D PDL_OFF
1416
1417// S34ML01G (Nand Flash) driver
1418#define PDL_UTILITY_ENABLE_EXTIF_S34ML01G PDL_OFF
1419
1420// TSDH1188 (Segment LCD) driver
1421#define PDL_UTILITY_ENABLE_SEG_LCD_TSDH1188 PDL_OFF
1422
1423// CL010-7031-04(Segment LCD) driver
1424#define PDL_UTILITY_ENABLE_SEG_LCD_CL0107031 PDL_OFF
1425
1426/**
1427 ******************************************************************************
1428 ** \brief Enable/disable print on the terminal window
1429 ******************************************************************************/
1430#define DEBUG_PRINT
1431
1432#endif // __PDL_USER_H__
1433
1434/******************************************************************************/
1435/* EOF (not truncated) */
1436/******************************************************************************/