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hw_layer
ports
stm32
stm32f7
cfg
mcuconf.h
Go to the documentation of this file.
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* STM32F7xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32F7xx_MCUCONF
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#define STM32F765_MCUCONF
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#define STM32F767_MCUCONF
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#define STM32F777_MCUCONF
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#define STM32F769_MCUCONF
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#define STM32F779_MCUCONF
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/* for stm32f746_nucleo */
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#define STM32F746_MCUCONF
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#include "efifeatures.h"
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/*
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* STM32F7xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32F7xx_MCUCONF
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// Allows LSE init to timeout and configure fallback RTC clock source in case
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#define RUSEFI_STM32_LSE_WAIT_MAX 1000000
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#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL STM32_RTCSEL_LSI
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/*
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* General settings.
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*/
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#define STM32_NO_INIT FALSE
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/*
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* Memory attributes settings.
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*/
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#ifndef STM32_NOCACHE_ENABLE
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#define STM32_NOCACHE_ENABLE TRUE
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#endif
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#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
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#define STM32_NOCACHE_RBAR SRAM2_BASE
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#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE TRUE
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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// see RUSEFI_STM32_LSE_WAIT_MAX
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#define STM32_LSE_ENABLED TRUE
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#define STM32_CLOCK48_REQUIRED TRUE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSI
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#define STM32_PLLM_VALUE 16
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#define STM32_PLLN_VALUE 432
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 9
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV4
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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// see RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL
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#define STM32_RTCSEL STM32_RTCSEL_LSE
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#define STM32_RTCPRE_VALUE 8
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
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#define STM32_I2SSRC STM32_I2SSRC_CKIN
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SP_VALUE 4
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PLLI2SR_VALUE 4
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#define STM32_PLLI2SDIVQ_VALUE 2
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#define STM32_PLLSAIN_VALUE 192
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#define STM32_PLLSAIP_VALUE 4
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#define STM32_PLLSAIQ_VALUE 4
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#define STM32_PLLSAIR_VALUE 4
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#define STM32_PLLSAIDIVQ_VALUE 2
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#define STM32_PLLSAIDIVR_VALUE 2
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#define STM32_SAI1SEL STM32_SAI1SEL_OFF
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#define STM32_SAI2SEL STM32_SAI2SEL_OFF
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#define STM32_LCDTFT_REQUIRED FALSE
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#define STM32_USART1SEL STM32_USART1SEL_PCLK2
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#define STM32_USART2SEL STM32_USART2SEL_PCLK1
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#define STM32_USART3SEL STM32_USART3SEL_PCLK1
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#define STM32_UART4SEL STM32_UART4SEL_PCLK1
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#define STM32_UART5SEL STM32_UART5SEL_PCLK1
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#define STM32_USART6SEL STM32_USART6SEL_PCLK2
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#define STM32_UART7SEL STM32_UART7SEL_PCLK1
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#define STM32_UART8SEL STM32_UART8SEL_PCLK1
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#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
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#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
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#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
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#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
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#define STM32_CECSEL STM32_CECSEL_LSE
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#define STM32_CK48MSEL STM32_CK48MSEL_PLL
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#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
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/*
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* GPT driver system settings.
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*/
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#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
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#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
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#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
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#define STM32_IRQ_TIM1_CC_PRIORITY 7
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#define STM32_IRQ_TIM2_PRIORITY 7
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#define STM32_IRQ_TIM3_PRIORITY 7
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#define STM32_IRQ_TIM4_PRIORITY 7
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#define STM32_IRQ_TIM5_PRIORITY 7
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#define STM32_IRQ_TIM6_PRIORITY 7
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#define STM32_IRQ_TIM7_PRIORITY 7
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#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
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#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
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#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
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#define STM32_IRQ_TIM8_CC_PRIORITY 7
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/*
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* SDC driver system settings.
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*/
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#define STM32_SDC_USE_SDMMC1 FALSE
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#define STM32_SDC_USE_SDMMC2 TRUE
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#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
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#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
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#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
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#define STM32_SDC_SDMMC_CLOCK_DELAY 10
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#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SDC_SDMMC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
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#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
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#define STM32_SDC_SDMMC2_DMA_PRIORITY 3
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#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
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#define STM32_SDC_SDMMC2_IRQ_PRIORITY 9
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#include "
mcuconf_common_f4_f7.h
"
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#endif
/* MCUCONF_H */
mcuconf_common_f4_f7.h
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