rusEFI
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hw_layer
ports
stm32
stm32f7
board.h
Go to the documentation of this file.
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* This file has been automatically generated using ChibiStudio board
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* generator plugin. Do not edit manually.
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*/
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#ifndef BOARD_H
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#define BOARD_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*
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* Board identifier.
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*/
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#define BOARD_ST_NUCLEO144_F767ZI
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#define BOARD_NAME "F7 for rusEFI"
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#define EFI_USB_AF 10U
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#define EFI_USB_SERIAL_DM Gpio::A11
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#define EFI_USB_SERIAL_DP Gpio::A12
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// Ignore USB VBUS pin (we're never a host, only a device)
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#define BOARD_OTG_NOVBUSSENS TRUE
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/*
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* Default to input mode, with internal pulldown resistor enabled.
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*/
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#define EFI_PIN_MODE_DEFAULT PIN_MODE_INPUT
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#ifndef EFI_DR_DEFAULT
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#define EFI_DR_DEFAULT PIN_PUPDR_PULLDOWN
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#endif
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// See https://github.com/rusefi/rusefi/issues/397
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#define DEFAULT_GPIO_SPEED PIN_OSPEED_HIGH
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/*
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* Ethernet PHY type.
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*/
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#define BOARD_PHY_ID MII_LAN8742A_ID
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#define BOARD_PHY_RMII
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/*
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* Default to input mode, with internal pulldown resistor enabled.
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*/
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#define EFI_PIN_MODE_DEFAULT PIN_MODE_INPUT
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#ifndef EFI_DR_DEFAULT
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#define EFI_DR_DEFAULT PIN_PUPDR_PULLDOWN
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#endif
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/*
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* Board oscillators-related settings.
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*/
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#if !defined(STM32_LSECLK)
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#define STM32_LSECLK 32768U
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#endif
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#define STM32_LSEDRV (3U << 3U)
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/*
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* Board voltages.
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* Required for performance limits calculation.
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*/
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#define STM32_VDD 300U
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/*
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* MCU type as defined in the ST header.
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*/
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#ifndef STM32F767xx
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#define STM32F767xx
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#endif
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/*
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* IO pins assignments.
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*/
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#define GPIOA_SWDIO 13
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#define GPIOA_SWCLK 14
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#define GPIOB_SWO 3
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/*
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* I/O ports initial setup, this configuration is established soon after reset
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* in the initialization code.
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* Please refer to the STM32 Reference Manual for details.
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*/
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#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
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#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
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#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
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#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
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#define PIN_ODR_LOW(n) (0U << (n))
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#define PIN_ODR_HIGH(n) (1U << (n))
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#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
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#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
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#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
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#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
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#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
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#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
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#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
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#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
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#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
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#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
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#define VAL_GPIO_MODER_ALL_DEFAULT (EFI_PIN_MODE_DEFAULT(0) | \
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EFI_PIN_MODE_DEFAULT(1) | \
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EFI_PIN_MODE_DEFAULT(2) | \
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EFI_PIN_MODE_DEFAULT(3) | \
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EFI_PIN_MODE_DEFAULT(4) | \
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EFI_PIN_MODE_DEFAULT(5) | \
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EFI_PIN_MODE_DEFAULT(6) | \
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EFI_PIN_MODE_DEFAULT(7) | \
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EFI_PIN_MODE_DEFAULT(8) | \
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EFI_PIN_MODE_DEFAULT(9) | \
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EFI_PIN_MODE_DEFAULT(10) | \
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EFI_PIN_MODE_DEFAULT(11) | \
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EFI_PIN_MODE_DEFAULT(12) | \
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EFI_PIN_MODE_DEFAULT(13) | \
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EFI_PIN_MODE_DEFAULT(14) | \
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EFI_PIN_MODE_DEFAULT(15))
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#define VAL_GPIO_OTYPER_ALL_DEFAULT (PIN_OTYPE_PUSHPULL(0) | \
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PIN_OTYPE_PUSHPULL(1) | \
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PIN_OTYPE_PUSHPULL(2) | \
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PIN_OTYPE_PUSHPULL(3) | \
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PIN_OTYPE_PUSHPULL(4) | \
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PIN_OTYPE_PUSHPULL(5) | \
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PIN_OTYPE_PUSHPULL(6) | \
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PIN_OTYPE_PUSHPULL(7) | \
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PIN_OTYPE_PUSHPULL(8) | \
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PIN_OTYPE_PUSHPULL(9) | \
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PIN_OTYPE_PUSHPULL(10) | \
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PIN_OTYPE_PUSHPULL(11) | \
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PIN_OTYPE_PUSHPULL(12) | \
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PIN_OTYPE_PUSHPULL(13) | \
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PIN_OTYPE_PUSHPULL(14) | \
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PIN_OTYPE_PUSHPULL(15))
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#define VAL_GPIO_OSPEEDR_ALL_DEFAULT (DEFAULT_GPIO_SPEED(0) | \
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DEFAULT_GPIO_SPEED(1) | \
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DEFAULT_GPIO_SPEED(2) | \
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DEFAULT_GPIO_SPEED(3) | \
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DEFAULT_GPIO_SPEED(4) | \
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DEFAULT_GPIO_SPEED(5) | \
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DEFAULT_GPIO_SPEED(6) | \
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DEFAULT_GPIO_SPEED(7) | \
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DEFAULT_GPIO_SPEED(8) | \
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DEFAULT_GPIO_SPEED(9) | \
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DEFAULT_GPIO_SPEED(10) | \
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DEFAULT_GPIO_SPEED(11) | \
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DEFAULT_GPIO_SPEED(12) | \
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DEFAULT_GPIO_SPEED(13) | \
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DEFAULT_GPIO_SPEED(14) | \
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DEFAULT_GPIO_SPEED(15))
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#define VAL_GPIO_ODR_ALL_DEFAULT 0
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#define VAL_GPIO_PUPDR_ALL_DEFAULT (EFI_DR_DEFAULT(0) | \
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EFI_DR_DEFAULT(1) | \
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EFI_DR_DEFAULT(2) | \
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EFI_DR_DEFAULT(3) | \
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EFI_DR_DEFAULT(4) | \
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EFI_DR_DEFAULT(5) | \
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EFI_DR_DEFAULT(6) | \
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EFI_DR_DEFAULT(7) | \
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EFI_DR_DEFAULT(8) | \
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EFI_DR_DEFAULT(9) | \
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EFI_DR_DEFAULT(10) | \
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EFI_DR_DEFAULT(11) | \
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EFI_DR_DEFAULT(12) | \
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EFI_DR_DEFAULT(13) | \
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EFI_DR_DEFAULT(14) | \
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EFI_DR_DEFAULT(15))
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#define VAL_GPIO_AF_ALL_DEFAULT (PIN_AFIO_AF(0, 0U) | \
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PIN_AFIO_AF(1, 0U) | \
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PIN_AFIO_AF(2, 0U) | \
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PIN_AFIO_AF(3, 0U) | \
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PIN_AFIO_AF(4, 0U) | \
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PIN_AFIO_AF(5, 0U) | \
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PIN_AFIO_AF(6, 0U) | \
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PIN_AFIO_AF(7, 0U))
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/*
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* GPIOA setup:
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*
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* PA11 - OTG_FS_DM (alternate 10).
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* PA12 - OTG_FS_DP (alternate 10).
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* PA13 - SWDIO (alternate 0).
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* PA14 - SWCLK (alternate 0).
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*/
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#define VAL_GPIOA_MODER (EFI_PIN_MODE_DEFAULT(0) | \
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EFI_PIN_MODE_DEFAULT(1) | \
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EFI_PIN_MODE_DEFAULT(2) | \
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EFI_PIN_MODE_DEFAULT(3) | \
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EFI_PIN_MODE_DEFAULT(4) | \
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EFI_PIN_MODE_DEFAULT(5) | \
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EFI_PIN_MODE_DEFAULT(6) | \
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EFI_PIN_MODE_DEFAULT(7) | \
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EFI_PIN_MODE_DEFAULT(8) | \
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EFI_PIN_MODE_DEFAULT(9) | \
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EFI_PIN_MODE_DEFAULT(10) | \
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PIN_MODE_ALTERNATE(11) | \
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PIN_MODE_ALTERNATE(12) | \
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PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
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PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
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EFI_PIN_MODE_DEFAULT(15))
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#define VAL_GPIOA_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
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#define VAL_GPIOA_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
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#define VAL_GPIOA_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
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#define VAL_GPIOA_ODR VAL_GPIO_ODR_ALL_DEFAULT
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#define VAL_GPIOA_AFRL (PIN_AFIO_AF(0, 0U) | \
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PIN_AFIO_AF(1, 0U) | \
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PIN_AFIO_AF(2, 0U) | \
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PIN_AFIO_AF(3, 0U) | \
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PIN_AFIO_AF(4, 6U) | \
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PIN_AFIO_AF(5, 5U) | \
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PIN_AFIO_AF(6, 5U) | \
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PIN_AFIO_AF(7, 5U))
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#define VAL_GPIOA_AFRH VAL_GPIO_AF_ALL_DEFAULT
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/*
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* GPIOB setup:
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*
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* Default except SWO configured on PB3
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*
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*/
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#define VAL_GPIOB_MODER (EFI_PIN_MODE_DEFAULT(0) | \
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EFI_PIN_MODE_DEFAULT(1) | \
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EFI_PIN_MODE_DEFAULT(2) | \
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PIN_MODE_ALTERNATE(GPIOB_SWO) | \
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EFI_PIN_MODE_DEFAULT(4) | \
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EFI_PIN_MODE_DEFAULT(5) | \
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EFI_PIN_MODE_DEFAULT(6) | \
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EFI_PIN_MODE_DEFAULT(7) | \
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EFI_PIN_MODE_DEFAULT(8) | \
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EFI_PIN_MODE_DEFAULT(9) | \
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EFI_PIN_MODE_DEFAULT(10) | \
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EFI_PIN_MODE_DEFAULT(11) | \
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EFI_PIN_MODE_DEFAULT(12) | \
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EFI_PIN_MODE_DEFAULT(13) | \
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EFI_PIN_MODE_DEFAULT(14) | \
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EFI_PIN_MODE_DEFAULT(15))
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#define VAL_GPIOB_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
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#define VAL_GPIOB_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
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#define VAL_GPIOB_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
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#define VAL_GPIOB_ODR VAL_GPIO_ODR_ALL_DEFAULT
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#define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0U) | \
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PIN_AFIO_AF(1, 0U) | \
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PIN_AFIO_AF(2, 0U) | \
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PIN_AFIO_AF(GPIOB_SWO, 0U) | \
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PIN_AFIO_AF(4, 0U) | \
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PIN_AFIO_AF(5, 0U) | \
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PIN_AFIO_AF(6, 0U) | \
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PIN_AFIO_AF(7, 0U))
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#define VAL_GPIOB_AFRH VAL_GPIO_AF_ALL_DEFAULT
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/*
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* GPIOC setup:
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*/
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#define VAL_GPIOC_MODER VAL_GPIO_MODER_ALL_DEFAULT
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#define VAL_GPIOC_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
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#define VAL_GPIOC_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
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#define VAL_GPIOC_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
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#define VAL_GPIOC_ODR VAL_GPIO_ODR_ALL_DEFAULT
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#define VAL_GPIOC_AFRL VAL_GPIO_AF_ALL_DEFAULT
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#define VAL_GPIOC_AFRH VAL_GPIO_AF_ALL_DEFAULT
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/*
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* GPIOD setup:
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*/
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#define VAL_GPIOD_MODER VAL_GPIO_MODER_ALL_DEFAULT
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#define VAL_GPIOD_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
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#define VAL_GPIOD_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
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#define VAL_GPIOD_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
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#define VAL_GPIOD_ODR VAL_GPIO_ODR_ALL_DEFAULT
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#define VAL_GPIOD_AFRL VAL_GPIO_AF_ALL_DEFAULT
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#define VAL_GPIOD_AFRH VAL_GPIO_AF_ALL_DEFAULT
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/*
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* GPIOE setup:
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*/
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#define VAL_GPIOE_MODER VAL_GPIO_MODER_ALL_DEFAULT
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#define VAL_GPIOE_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
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#define VAL_GPIOE_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
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#define VAL_GPIOE_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
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#define VAL_GPIOE_ODR VAL_GPIO_ODR_ALL_DEFAULT
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#define VAL_GPIOE_AFRL VAL_GPIO_AF_ALL_DEFAULT
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#define VAL_GPIOE_AFRH VAL_GPIO_AF_ALL_DEFAULT
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/*
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* GPIOF setup:
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*/
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#define VAL_GPIOF_MODER VAL_GPIO_MODER_ALL_DEFAULT
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#define VAL_GPIOF_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
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#define VAL_GPIOF_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
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#define VAL_GPIOF_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
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#define VAL_GPIOF_ODR VAL_GPIO_ODR_ALL_DEFAULT
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#define VAL_GPIOF_AFRL VAL_GPIO_AF_ALL_DEFAULT
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#define VAL_GPIOF_AFRH VAL_GPIO_AF_ALL_DEFAULT
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/*
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* GPIOG setup:
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*/
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#define VAL_GPIOG_MODER VAL_GPIO_MODER_ALL_DEFAULT
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#define VAL_GPIOG_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
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#define VAL_GPIOG_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
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#define VAL_GPIOG_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
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#define VAL_GPIOG_ODR VAL_GPIO_ODR_ALL_DEFAULT
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#define VAL_GPIOG_AFRL VAL_GPIO_AF_ALL_DEFAULT
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#define VAL_GPIOG_AFRH VAL_GPIO_AF_ALL_DEFAULT
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/*
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* GPIOH setup:
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*/
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#define VAL_GPIOH_MODER VAL_GPIO_MODER_ALL_DEFAULT
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#define VAL_GPIOH_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
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#define VAL_GPIOH_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
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#define VAL_GPIOH_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
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#define VAL_GPIOH_ODR VAL_GPIO_ODR_ALL_DEFAULT
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#define VAL_GPIOH_AFRL VAL_GPIO_AF_ALL_DEFAULT
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#define VAL_GPIOH_AFRH VAL_GPIO_AF_ALL_DEFAULT
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/*
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* GPIOI setup:
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*/
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#define VAL_GPIOI_MODER VAL_GPIO_MODER_ALL_DEFAULT
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#define VAL_GPIOI_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
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#define VAL_GPIOI_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
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#define VAL_GPIOI_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
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#define VAL_GPIOI_ODR VAL_GPIO_ODR_ALL_DEFAULT
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#define VAL_GPIOI_AFRL VAL_GPIO_AF_ALL_DEFAULT
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#define VAL_GPIOI_AFRH VAL_GPIO_AF_ALL_DEFAULT
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/*
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* GPIOJ setup:
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*/
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#define VAL_GPIOJ_MODER VAL_GPIO_MODER_ALL_DEFAULT
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#define VAL_GPIOJ_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
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#define VAL_GPIOJ_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
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#define VAL_GPIOJ_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
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#define VAL_GPIOJ_ODR VAL_GPIO_ODR_ALL_DEFAULT
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#define VAL_GPIOJ_AFRL VAL_GPIO_AF_ALL_DEFAULT
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#define VAL_GPIOJ_AFRH VAL_GPIO_AF_ALL_DEFAULT
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/*
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* GPIOK setup:
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*/
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#define VAL_GPIOK_MODER VAL_GPIO_MODER_ALL_DEFAULT
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#define VAL_GPIOK_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
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#define VAL_GPIOK_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
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#define VAL_GPIOK_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
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#define VAL_GPIOK_ODR VAL_GPIO_ODR_ALL_DEFAULT
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#define VAL_GPIOK_AFRL VAL_GPIO_AF_ALL_DEFAULT
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#define VAL_GPIOK_AFRH VAL_GPIO_AF_ALL_DEFAULT
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#endif
/* BOARD_H */
Generated on Sat Sep 27 2025 00:10:07 for rusEFI by
1.9.8
1.9.8