rusEFI
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board.h
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1/*
2 ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * This file has been automatically generated using ChibiStudio board
19 * generator plugin. Do not edit manually.
20 */
21
22#ifndef BOARD_H
23#define BOARD_H
24/*
25 * Board identifier.
26 */
27#define BOARD_NAME "F4 for rusEFI"
28
29#define EFI_USB_AF 10U
30#define EFI_USB_SERIAL_DM Gpio::A11
31#define EFI_USB_SERIAL_DP Gpio::A12
32
33// Ignore USB VBUS pin (we're never a host, only a device)
34#define BOARD_OTG_NOVBUSSENS TRUE
35
36/*
37 * Ethernet PHY type.
38 */
39#define BOARD_PHY_ID MII_LAN8742A_ID
40#define BOARD_PHY_RMII
41
42/*
43 * Default to input mode, with internal pulldown resistor enabled.
44 */
45#define EFI_PIN_MODE_DEFAULT PIN_MODE_INPUT
46#ifndef EFI_DR_DEFAULT
47#define EFI_DR_DEFAULT PIN_PUPDR_PULLDOWN
48#endif
49
50// See https://github.com/rusefi/rusefi/issues/397
51#define DEFAULT_GPIO_SPEED PIN_OSPEED_HIGH
52
53/*
54 * Board oscillators-related settings.
55 * NOTE: LSE not fitted.
56 */
57#if !defined(STM32_LSECLK)
58#define STM32_LSECLK 32768U
59#endif
60
61/*
62 * Board voltages.
63 * Required for performance limits calculation.
64 */
65#define STM32_VDD 300U
66
67/*
68 * IO pins assignments.
69 */
70#define GPIOA_SWDIO 13
71#define GPIOA_SWCLK 14
72
73#define GPIOB_SWO 3
74
75/*
76 * I/O ports initial setup, this configuration is established soon after reset
77 * in the initialization code.
78 * Please refer to the STM32 Reference Manual for details.
79 */
80#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
81#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
82#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
83#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
84#define PIN_ODR_LOW(n) (0U << (n))
85#define PIN_ODR_HIGH(n) (1U << (n))
86#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
87#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
88#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
89#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
90#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
91#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
92#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
93#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
94#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
95#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
96
97#define VAL_GPIO_MODER_ALL_DEFAULT (EFI_PIN_MODE_DEFAULT(0) | \
98 EFI_PIN_MODE_DEFAULT(1) | \
99 EFI_PIN_MODE_DEFAULT(2) | \
100 EFI_PIN_MODE_DEFAULT(3) | \
101 EFI_PIN_MODE_DEFAULT(4) | \
102 EFI_PIN_MODE_DEFAULT(5) | \
103 EFI_PIN_MODE_DEFAULT(6) | \
104 EFI_PIN_MODE_DEFAULT(7) | \
105 EFI_PIN_MODE_DEFAULT(8) | \
106 EFI_PIN_MODE_DEFAULT(9) | \
107 EFI_PIN_MODE_DEFAULT(10) | \
108 EFI_PIN_MODE_DEFAULT(11) | \
109 EFI_PIN_MODE_DEFAULT(12) | \
110 EFI_PIN_MODE_DEFAULT(13) | \
111 EFI_PIN_MODE_DEFAULT(14) | \
112 EFI_PIN_MODE_DEFAULT(15))
113
114#define VAL_GPIO_OTYPER_ALL_DEFAULT (PIN_OTYPE_PUSHPULL(0) | \
115 PIN_OTYPE_PUSHPULL(1) | \
116 PIN_OTYPE_PUSHPULL(2) | \
117 PIN_OTYPE_PUSHPULL(3) | \
118 PIN_OTYPE_PUSHPULL(4) | \
119 PIN_OTYPE_PUSHPULL(5) | \
120 PIN_OTYPE_PUSHPULL(6) | \
121 PIN_OTYPE_PUSHPULL(7) | \
122 PIN_OTYPE_PUSHPULL(8) | \
123 PIN_OTYPE_PUSHPULL(9) | \
124 PIN_OTYPE_PUSHPULL(10) | \
125 PIN_OTYPE_PUSHPULL(11) | \
126 PIN_OTYPE_PUSHPULL(12) | \
127 PIN_OTYPE_PUSHPULL(13) | \
128 PIN_OTYPE_PUSHPULL(14) | \
129 PIN_OTYPE_PUSHPULL(15))
130
131#define VAL_GPIO_OSPEEDR_ALL_DEFAULT (DEFAULT_GPIO_SPEED(0) | \
132 DEFAULT_GPIO_SPEED(1) | \
133 DEFAULT_GPIO_SPEED(2) | \
134 DEFAULT_GPIO_SPEED(3) | \
135 DEFAULT_GPIO_SPEED(4) | \
136 DEFAULT_GPIO_SPEED(5) | \
137 DEFAULT_GPIO_SPEED(6) | \
138 DEFAULT_GPIO_SPEED(7) | \
139 DEFAULT_GPIO_SPEED(8) | \
140 DEFAULT_GPIO_SPEED(9) | \
141 DEFAULT_GPIO_SPEED(10) | \
142 DEFAULT_GPIO_SPEED(11) | \
143 DEFAULT_GPIO_SPEED(12) | \
144 DEFAULT_GPIO_SPEED(13) | \
145 DEFAULT_GPIO_SPEED(14) | \
146 DEFAULT_GPIO_SPEED(15))
147
148#define VAL_GPIO_ODR_ALL_DEFAULT 0
149
150#define VAL_GPIO_PUPDR_ALL_DEFAULT (EFI_DR_DEFAULT(0) | \
151 EFI_DR_DEFAULT(1) | \
152 EFI_DR_DEFAULT(2) | \
153 EFI_DR_DEFAULT(3) | \
154 EFI_DR_DEFAULT(4) | \
155 EFI_DR_DEFAULT(5) | \
156 EFI_DR_DEFAULT(6) | \
157 EFI_DR_DEFAULT(7) | \
158 EFI_DR_DEFAULT(8) | \
159 EFI_DR_DEFAULT(9) | \
160 EFI_DR_DEFAULT(10) | \
161 EFI_DR_DEFAULT(11) | \
162 EFI_DR_DEFAULT(12) | \
163 EFI_DR_DEFAULT(13) | \
164 EFI_DR_DEFAULT(14) | \
165 EFI_DR_DEFAULT(15))
166
167#define VAL_GPIO_AF_ALL_DEFAULT (PIN_AFIO_AF(0, 0U) | \
168 PIN_AFIO_AF(1, 0U) | \
169 PIN_AFIO_AF(2, 0U) | \
170 PIN_AFIO_AF(3, 0U) | \
171 PIN_AFIO_AF(4, 0U) | \
172 PIN_AFIO_AF(5, 0U) | \
173 PIN_AFIO_AF(6, 0U) | \
174 PIN_AFIO_AF(7, 0U))
175
176
177/*
178 * GPIOA setup:
179 *
180 * PA11 - OTG_FS_DM (alternate 10).
181 * PA12 - OTG_FS_DP (alternate 10).
182 * PA13 - SWDIO (alternate 0).
183 * PA14 - SWCLK (alternate 0).
184 */
185#define VAL_GPIOA_MODER (EFI_PIN_MODE_DEFAULT(0) | \
186 EFI_PIN_MODE_DEFAULT(1) | \
187 EFI_PIN_MODE_DEFAULT(2) | \
188 EFI_PIN_MODE_DEFAULT(3) | \
189 EFI_PIN_MODE_DEFAULT(4) | \
190 EFI_PIN_MODE_DEFAULT(5) | \
191 EFI_PIN_MODE_DEFAULT(6) | \
192 EFI_PIN_MODE_DEFAULT(7) | \
193 EFI_PIN_MODE_DEFAULT(8) | \
194 EFI_PIN_MODE_DEFAULT(9) | \
195 EFI_PIN_MODE_DEFAULT(10) | \
196 PIN_MODE_ALTERNATE(11) | \
197 PIN_MODE_ALTERNATE(12) | \
198 PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
199 PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
200 EFI_PIN_MODE_DEFAULT(15))
201#define VAL_GPIOA_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
202#define VAL_GPIOA_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
203#define VAL_GPIOA_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
204#define VAL_GPIOA_ODR VAL_GPIO_ODR_ALL_DEFAULT
205#define VAL_GPIOA_AFRL (PIN_AFIO_AF(0, 0U) | \
206 PIN_AFIO_AF(1, 0U) | \
207 PIN_AFIO_AF(2, 0U) | \
208 PIN_AFIO_AF(3, 0U) | \
209 PIN_AFIO_AF(4, 6U) | \
210 PIN_AFIO_AF(5, 5U) | \
211 PIN_AFIO_AF(6, 5U) | \
212 PIN_AFIO_AF(7, 5U))
213#define VAL_GPIOA_AFRH VAL_GPIO_AF_ALL_DEFAULT
214
215/*
216 * GPIOB setup:
217 *
218 * Default except SWO configured on PB3
219 *
220 */
221#define VAL_GPIOB_MODER (EFI_PIN_MODE_DEFAULT(0) | \
222 EFI_PIN_MODE_DEFAULT(1) | \
223 EFI_PIN_MODE_DEFAULT(2) | \
224 PIN_MODE_ALTERNATE(GPIOB_SWO) | \
225 EFI_PIN_MODE_DEFAULT(4) | \
226 EFI_PIN_MODE_DEFAULT(5) | \
227 EFI_PIN_MODE_DEFAULT(6) | \
228 EFI_PIN_MODE_DEFAULT(7) | \
229 EFI_PIN_MODE_DEFAULT(8) | \
230 EFI_PIN_MODE_DEFAULT(9) | \
231 EFI_PIN_MODE_DEFAULT(10) | \
232 EFI_PIN_MODE_DEFAULT(11) | \
233 EFI_PIN_MODE_DEFAULT(12) | \
234 EFI_PIN_MODE_DEFAULT(13) | \
235 EFI_PIN_MODE_DEFAULT(14) | \
236 EFI_PIN_MODE_DEFAULT(15))
237#define VAL_GPIOB_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
238#define VAL_GPIOB_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
239#define VAL_GPIOB_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
240#define VAL_GPIOB_ODR VAL_GPIO_ODR_ALL_DEFAULT
241#define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0U) | \
242 PIN_AFIO_AF(1, 0U) | \
243 PIN_AFIO_AF(2, 0U) | \
244 PIN_AFIO_AF(GPIOB_SWO, 0U) | \
245 PIN_AFIO_AF(4, 0U) | \
246 PIN_AFIO_AF(5, 0U) | \
247 PIN_AFIO_AF(6, 0U) | \
248 PIN_AFIO_AF(7, 0U))
249#define VAL_GPIOB_AFRH VAL_GPIO_AF_ALL_DEFAULT
250
251/*
252 * GPIOC setup:
253 */
254#define VAL_GPIOC_MODER VAL_GPIO_MODER_ALL_DEFAULT
255#define VAL_GPIOC_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
256#define VAL_GPIOC_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
257#define VAL_GPIOC_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
258#define VAL_GPIOC_ODR VAL_GPIO_ODR_ALL_DEFAULT
259#define VAL_GPIOC_AFRL VAL_GPIO_AF_ALL_DEFAULT
260#define VAL_GPIOC_AFRH VAL_GPIO_AF_ALL_DEFAULT
261
262/*
263 * GPIOD setup:
264 */
265#define VAL_GPIOD_MODER VAL_GPIO_MODER_ALL_DEFAULT
266#define VAL_GPIOD_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
267#define VAL_GPIOD_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
268#define VAL_GPIOD_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
269#define VAL_GPIOD_ODR VAL_GPIO_ODR_ALL_DEFAULT
270#define VAL_GPIOD_AFRL VAL_GPIO_AF_ALL_DEFAULT
271#define VAL_GPIOD_AFRH VAL_GPIO_AF_ALL_DEFAULT
272
273/*
274 * GPIOE setup:
275 */
276#define VAL_GPIOE_MODER VAL_GPIO_MODER_ALL_DEFAULT
277#define VAL_GPIOE_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
278#define VAL_GPIOE_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
279#define VAL_GPIOE_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
280#define VAL_GPIOE_ODR VAL_GPIO_ODR_ALL_DEFAULT
281#define VAL_GPIOE_AFRL VAL_GPIO_AF_ALL_DEFAULT
282#define VAL_GPIOE_AFRH VAL_GPIO_AF_ALL_DEFAULT
283
284/*
285 * GPIOF setup:
286 */
287#define VAL_GPIOF_MODER VAL_GPIO_MODER_ALL_DEFAULT
288#define VAL_GPIOF_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
289#define VAL_GPIOF_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
290#define VAL_GPIOF_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
291#define VAL_GPIOF_ODR VAL_GPIO_ODR_ALL_DEFAULT
292#define VAL_GPIOF_AFRL VAL_GPIO_AF_ALL_DEFAULT
293#define VAL_GPIOF_AFRH VAL_GPIO_AF_ALL_DEFAULT
294
295/*
296 * GPIOG setup:
297 */
298#define VAL_GPIOG_MODER VAL_GPIO_MODER_ALL_DEFAULT
299#define VAL_GPIOG_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
300#define VAL_GPIOG_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
301#define VAL_GPIOG_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
302#define VAL_GPIOG_ODR VAL_GPIO_ODR_ALL_DEFAULT
303#define VAL_GPIOG_AFRL VAL_GPIO_AF_ALL_DEFAULT
304#define VAL_GPIOG_AFRH VAL_GPIO_AF_ALL_DEFAULT
305
306/*
307 * GPIOH setup:
308 */
309#define VAL_GPIOH_MODER VAL_GPIO_MODER_ALL_DEFAULT
310#define VAL_GPIOH_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
311#define VAL_GPIOH_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
312#define VAL_GPIOH_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
313#define VAL_GPIOH_ODR VAL_GPIO_ODR_ALL_DEFAULT
314#define VAL_GPIOH_AFRL VAL_GPIO_AF_ALL_DEFAULT
315#define VAL_GPIOH_AFRH VAL_GPIO_AF_ALL_DEFAULT
316
317/*
318 * GPIOI setup:
319 */
320#define VAL_GPIOI_MODER VAL_GPIO_MODER_ALL_DEFAULT
321#define VAL_GPIOI_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
322#define VAL_GPIOI_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
323#define VAL_GPIOI_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
324#define VAL_GPIOI_ODR VAL_GPIO_ODR_ALL_DEFAULT
325#define VAL_GPIOI_AFRL VAL_GPIO_AF_ALL_DEFAULT
326#define VAL_GPIOI_AFRH VAL_GPIO_AF_ALL_DEFAULT
327
328#endif /* BOARD_H */
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